A 27-mW 3.6-Gb/s I/O transceiver

Wong, K.-L.J.; Mansuri, M.; Hatamkhani, H.; Yang, Chih-Kong Ken

doi:10.1109/vlsic.2003.1221173

Cited by 24 publications

(31 citation statements)

References 6 publications

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“…In this implementation, we targeted 6 Gb/s operation. The output multiplexer is a current-mode logic (CML) stage which is linear, operates at a low supply voltage, and has a relatively fixed largesignal output impedance to avoid source reflections present in some low-power transmit schemes [10].…”

Section: Circuit Implementationmentioning

confidence: 99%

“…Transmitters must drive enough power over lossy interconnects to meet minimum receiver sensitivity requirements. Finding new methods to lower power consumption in serial links has been explored through low-common-mode signaling [10] and through low-supply operation [11]. Amplitude pre-emphasis distorts the signal to compensate ISI introduced by the bandwidth limitations of the interconnect [12], [13].…”

mentioning

confidence: 99%

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Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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Abstract-A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase preemphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6 Gb/s and 600 mVpp output swing, a power budget of 3 mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24 mW, a budget of 4 mW/Gb/s.

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Section: Circuit Implementationmentioning

confidence: 99%

mentioning

confidence: 99%

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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“…In [9], we solve for the variation in the threshold crossing time as a function of the pole location, the voltage threshold, and the particular bit sequence. The threshold crossing time is (3) where is a parameter that relates the cutoff frequency and the bit rate, . Fig.…”

Section: A Single Pole Responsementioning

confidence: 99%

“…To develop an expression for the separation between the two dominant DDJ peaks, we calculate the mean for several data sequences using (3). The DDJ is quantified by this separation and is referred to by .…”

Section: A Single Pole Responsementioning

confidence: 99%

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Analysis and Equalization of Data-Dependent Jitter

Buckwalter

Hajimiri

2006

IEEE J. Solid-State Circuits

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Abstract-Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase-and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10 12 BER from 30 to 52 ps at 10 Gb/s.

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Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

Rao

Mandal

2010

Circuit Theory & Apps

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In this work, we propose transmitter and receiver circuits for high-speed, low-swing duobinary signaling over active-terminated chip-to-chip interconnect. In active-termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High-speed current-mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx-Rx pair is used to validate the proposed active-termination scheme. We also propose a duobinary precoder architecture suitable for high-speed operation and a low-power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 m Digital CMOS technology. The designed high-speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10 −15 . The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s.

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A 27-mW 3.6-Gb/s I/O transceiver

Cited by 24 publications

References 6 publications

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Analysis and Equalization of Data-Dependent Jitter

Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

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