Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Abstract

Abstract-A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase preemphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6 Gb/s and 600 mVpp output swing, a power budget of 3 mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24 mW, a budget of 4 mW/Gb/s.

ISI mitigation using bit-edge equalization in high-speed backplane data transmission

“…The difficulty in phase-optimized edge equalization is that the reference zero crossing points will shift in time with different data patterns and transmission rates. Therefore, complicated algorithms are required to achieve phase equalization [11], [12].…”

“…Previous publications [9]- [12] have shown that edge equalization enlarges eye width and hence the data eye is more tolerable to random jitter. However, in those previous publications, researchers again took the centers of the bit time periods as the optimal bit center sampling points, and 0.5 unit interval (UI) away from the centers of the bit time periods as the optimal bit edge sampling points.…”

Using bit-edge equalization in highspeed backplane data transmission

“…The difficulty in phase-optimized edge equalization is that the reference zero crossing points will shift in time with different data patterns and transmission rates. Therefore, complicated algorithms are required to achieve phase equalization [10], [11].…”

“…Previous publications [8]- [11] have shown that edge equalization reduces ISI at bit edges. However, in those previous publications, researchers again took the centers of the bit time periods as the optimal bit center sampling points, and 0.5 unit interval (UI) away from the centers of the bit time periods as the optimal bit edge sampling points.…”

On-chip data communication : analysis, optimization and circuit design

“…Half-symbol spaced delays can for example be used, which gives an additional degree of freedom to also cancel ISI at the zero-crossings [118,119], thereby minimizing the so-called datadependent jitter [118] and opening the eye in the horizontal direction.…”