A 10-mW 3.6-Gbps I/O transmitter

Abstract

The swing at the output of the driver is determined by This paper describes a low-power self-terminated the attenuation of the channel and the sensitivity of the transmitter. A novel architecture is proposed to perform receiver. In this design the target sensitivity of the receiver is impedance matching and channel equalization with low <35mV. The pre-distortion design handles 14dB loss of 6.5 power consumption. The test chip is fabricated using 0.18-pm meters of RG55 or 80 centimeters of FR-4 20 mils PCB at digital CMOS process with 1.8-V supply. The transmitter 1.8GHz. operates at 3.6Gbps and consumes 9.66mW. The total NMOS devices are used for both pull-up and pull-down transmitter area is 0.072 mm2.to minimize device size and capacitance. The source Abstract This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2mmz in a 0.18-um 1.8-V CMOS technology.

An Energy-Efficient Equalized Transceiver for RC-Dominant Channels

“…Before we explain the CI FFE driver, we introduce a current switching (CS) driver to more easily compare the CI FFE driver and a conventional voltage dividing (VD) driver [12]- [14], which is known to be more power efficient than a current mode logic (CML) driver [13]. The VD driver implements the FFE function via programmable resistive voltage divider while the CS driver adds/subtracts currents as shown in Fig.…”

“…These high losses show the good robustness of the CI FFE compared to other on-chip links [6]- [8]. Additionally, in off-chip links with conventional FFE [11], [12], [15] losses up to 30 dB are typically considered equalizable. Fig.…”

Equalized interconnects for on-chip networks: modeling and optimization framework

“…When different segments are driven with delayed data, this driver becomes an analog FIR filter [12], which can be used as an FFE. At the link model layer, our tool uses the linearized LCM model as a controlled voltage source with impedance R s and parasitic capacitance C s that captures the transient response of the LCM driver.…”

“…This is a shortcoming of the LCM drivers and indicates room for further improvement at the circuit level. Note that in on-chip applications, even with this static power component, LCM drivers are a lot more efficient than high-common mode differential pair drivers [12].…”

A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level

“…As the data rate increases, the inter-symbol interference (ISI) becomes much more sever and the signal equalization of a receiver may not be sufficient to get enough eye opening and the pre-emphasis of transmitted signal level is often required. The pre-emphasis is usually achieved by employing a sub-driver which may increase or decrease the transmitted signal level depending on the pattern [7,8]. The required level of pre-emphasis can be different depending on the channel loss and thus the sub-driver of a voltage-mode driver must have variable strength.…”