A 27-mW 3.6-Gb/s I/O Transceiver

Wong, K.-L.J.; Hatamkhani, H.; Mansuri, M.; Yang, Chih-Kong Ken

doi:10.1109/jssc.2004.825259

Cited by 108 publications

(9 citation statements)

References 11 publications

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“…The proposed 2-tap transmitter shows better energy efficiency compared with the previous works even with high equalisation. Magnitude of equalisation is not presented in [3] Conclusion: In this Letter, a 5 Gbit/s 2-tap low-swing voltage-mode transmitter is proposed. The proposed 2-tap transmitter compensates the channel loss at high frequency and provides well-matched output impedance.…”

Section: Fig 2 Schematic Diagram Of Proposed Iccmentioning

confidence: 97%

5 Gbit/s 2‐tap low‐swing voltage‐mode transmitter with least segmented voltage‐mode equalisation

2014

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A 2-tap low-swing voltage-mode transmitter which compensates the loss of channel at high frequency is proposed. The output driver of the proposed 2-tap transmitter consists of only two voltage-mode drivers, and thereby the design complexity of the pre-driver is greatly reduced compared with that of conventional 2 N -segmented voltage-mode drivers, where N is the number of equalisation control bits. The output impedance of each voltage-mode driver is adjusted not only to make the overall output impedance matched with the characteristic impedance of the channel, but also to achieve the desired equalisation coefficient by adopting the proposed calibration circuitry. With a high equalisation coefficient, the proposed output driver consumes less power compared with the hybrid voltage-mode driver with current-mode equalisation. The proposed transmitter is implemented using a 90 nm low-power CMOS process technology and achieves 0.79 pJ/bit without equalisation and 0.98 pJ/bit with 6 dB equalisation, at the data rate of 5 Gbit/s. Introduction: As the data rate required for chip-to-chip communications increases, the demand for a low-power (LP) serial link also increases to reduce the overall system power consumption. Among various components in the LP serial link, the output driver of the transmitter often consumes large power in order to drive the low-impedance channel with adequate signal swing [1]. Since the voltage-mode driver consumes only a quarter of power compared with the current-mode driver, it is frequently exploited in recent LP serial-link transmitters [2].For several giga-bit-per-second data transmissions, a transmitter equalisation is adopted to compensate the loss of channel at high frequency. A segmented output driver [3] has been conventionally used to implement the transmitter equalisation into the voltage-mode driver. For the equalisation with N-bit resolution, 2 N -segmented output drivers are required, resulting in an increase in the complexity and dynamic power consumption of the pre-driver and selection logics. The hybrid voltage-mode driver with current-mode equalisation [1] is used to eliminate 2 N -segmented output drivers, and thereby significantly reducing the complexity and power of the pre-driver. However, the hybrid driver requires a higher supply voltage to operate transistors of the current-mode equalisation branch in the saturation region. As the equalisation coefficient increases, the current flowing through the current-mode equalisation branch also increases, resulting in an increase in the power consumption of the output driver. In this Letter, we propose the voltage-mode output driver with the least segmented voltage-mode equalisation to reduce the complexity and power of the pre-driver. In addition, the proposed output driver consumes less power at a high equalisation coefficient.

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Section: Fig 2 Schematic Diagram Of Proposed Iccmentioning

confidence: 97%

5 Gbit/s 2‐tap low‐swing voltage‐mode transmitter with least segmented voltage‐mode equalisation

2014

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“…Especially, the clock buffer, which delivers the fastest signal to the largest load in the TX chip, dissipates a large amount of power. Therefore, parallel-clocking architecture, which is optimized to minimize the inter-chip clocking overhead, enhances the energy and area efficiencies of the TX [10], [11]. A fanoutof-four (FO4) CMOS inverter-chain, which provides minimal delay and energy efficiency to drive a certain capacitive load, can be used as the clock buffer at low clock frequencies.…”

Section: A Optimal Clocking Architecture For a 40 Gb/s Serial Link Tmentioning

confidence: 99%

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

Bae

Park

et al. 2016

IEEE J. Solid-State Circuits

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This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverterbased frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm 2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-ofmerit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB. Index Terms-CMOS, jitter, phase-locked loop (PLL), ring oscillator, serial link transmitter.

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“…have separate SerDes on the router chip where some of the SerDes are used to drive local links while others are used to drive global links and reduce the power consumption. For example, a SerDes that can drive <1m of backplane only consumes approximately 40mW [32] (P link ll ), resulting in over 5x power reduction. The different power assumptions are summarized in Table 5 and the power comparison for the different topologies are shown in Figure 15.…”

Section: Power Comparisonmentioning

confidence: 99%

Flattened butterfly

Kim

Dally

Abts³

2007

SIGARCH Comput. Archit. News

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Increasing integrated-circuit pin bandwidth has motivated a corresponding increase in the degree or radix of interconnection networks and their routers. This paper introduces the flattened butterfly, a cost-efficient topology for highradix networks. On benign (load-balanced) traffic, the flattened butterfly approaches the cost/performance of a butterfly network and has roughly half the cost of a comparable performance Clos network. The advantage over the Clos is achieved by eliminating redundant hops when they are not needed for load balance. On adversarial traffic, the flattened butterfly matches the cost/performance of a folded-Clos network and provides an order of magnitude better performance than a conventional butterfly. In this case, global adaptive routing is used to switch the flattened butterfly from minimal to non-minimal routing -using redundant hops only when they are needed. Minimal and non-minimal, oblivious and adaptive routing algorithms are evaluated on the flattened butterfly. We show that load-balancing adversarial traffic requires non-minimal globally-adaptive routing and show that sequential allocators are required to avoid transient load imbalance when using adaptive routing algorithms. We also compare the cost of the flattened butterfly to folded-Clos, hypercube, and butterfly networks with identical capacity and show that the flattened butterfly is more cost-efficient than folded-Clos and hypercube topologies.

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A 27-mW 3.6-Gb/s I/O Transceiver

Cited by 108 publications

References 11 publications

5 Gbit/s 2‐tap low‐swing voltage‐mode transmitter with least segmented voltage‐mode equalisation

5 Gbit/s 2‐tap low‐swing voltage‐mode transmitter with least segmented voltage‐mode equalisation

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

Flattened butterfly

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