In this letter, we propose a compensation method for organic light-emitting diode (OLED) degradation occurring in a digital driving scheme for active-matrix OLED displays. The proposed method, in which we are the first to propose, employs the modified stretched exponential decay (SED) model to characterize the OLED degradation and compensates for the associated luminance decrease; the lifetime of an OLED panel can thereby be extended. The OLED panel is fabricated using low-temperature poly-Si thin-film transistors, and measured to verify the modified SED model and the proposed compensation method. The measurement results show that the luminance degradation with and without the proposed method is 0.3% and 6%, 4% and 17.8%, and 7.4% and 30.4%, for red, green, and blue OLEDs, respectively. This measurement is taken after 40 h of operation under a 350 cd/m 2 initial luminance. Accordingly, the proposed compensation method extends the lifetime of the OLED panel up to 72.5, 15.5, and 20.75 times longer in red, green, and blue OLEDs, respectively, compared with the conventional method. IndexTerms-OLED degradation, digital driving, compensation, AMOLED, stretched exponential decay model, lifetime extension of AMOLED.
This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.
A 2-tap low-swing voltage-mode transmitter which compensates the loss of channel at high frequency is proposed. The output driver of the proposed 2-tap transmitter consists of only two voltage-mode drivers, and thereby the design complexity of the pre-driver is greatly reduced compared with that of conventional 2 N -segmented voltage-mode drivers, where N is the number of equalisation control bits. The output impedance of each voltage-mode driver is adjusted not only to make the overall output impedance matched with the characteristic impedance of the channel, but also to achieve the desired equalisation coefficient by adopting the proposed calibration circuitry. With a high equalisation coefficient, the proposed output driver consumes less power compared with the hybrid voltage-mode driver with current-mode equalisation. The proposed transmitter is implemented using a 90 nm low-power CMOS process technology and achieves 0.79 pJ/bit without equalisation and 0.98 pJ/bit with 6 dB equalisation, at the data rate of 5 Gbit/s. Introduction: As the data rate required for chip-to-chip communications increases, the demand for a low-power (LP) serial link also increases to reduce the overall system power consumption. Among various components in the LP serial link, the output driver of the transmitter often consumes large power in order to drive the low-impedance channel with adequate signal swing [1]. Since the voltage-mode driver consumes only a quarter of power compared with the current-mode driver, it is frequently exploited in recent LP serial-link transmitters [2].For several giga-bit-per-second data transmissions, a transmitter equalisation is adopted to compensate the loss of channel at high frequency. A segmented output driver [3] has been conventionally used to implement the transmitter equalisation into the voltage-mode driver. For the equalisation with N-bit resolution, 2 N -segmented output drivers are required, resulting in an increase in the complexity and dynamic power consumption of the pre-driver and selection logics. The hybrid voltage-mode driver with current-mode equalisation [1] is used to eliminate 2 N -segmented output drivers, and thereby significantly reducing the complexity and power of the pre-driver. However, the hybrid driver requires a higher supply voltage to operate transistors of the current-mode equalisation branch in the saturation region. As the equalisation coefficient increases, the current flowing through the current-mode equalisation branch also increases, resulting in an increase in the power consumption of the output driver. In this Letter, we propose the voltage-mode output driver with the least segmented voltage-mode equalisation to reduce the complexity and power of the pre-driver. In addition, the proposed output driver consumes less power at a high equalisation coefficient.
This paper proposes a highly reliable single-inductor multi-output (SIMO) converter for energy harvesting systems, which is controlled by the power management controller (PMC) including the hybrid starter, overcharging protector (OCP), and switch controller (SWC). The proposed hybrid starter employs the power-on-reset to accurately control the activated and deactivated moments of the SWC, thus generating a system supply voltage (VSYS) within the stable operating voltage range. The proposed OCP employs the diode-connection and Schmitt trigger schemes to monitor the voltage of a storage device (VSTG) in real time, thereby protecting the IC from being damaged without using either a capacitor or Zener diode, which causes the additional area or reverse leakage current, respectively. The proposed SIMO converter with the PMC was fabricated using 0.18-µm CMOS process. The measurement results show that VSYS values at the activated and deactivated moments of the SWC are 1.798 V and 1.510 V, respectively, both of which are within the stable system voltage range for 1.8 V devices. In addition, the measured maximum VSTG is 5.892 V, which is much lower than an absolute maximum rated voltage of 9.2 V for 5 V devices. Furthermore, the measurement results reveal that the hybrid starter allows the proposed SIMO converter to be properly restarted immediately after VSYS is shorted to ground, while the OCP safely protects the SIMO converter even when the storage device is removed from the IC while charging. Therefore, the proposed SIMO converter with the PMC is suitable for energy harvesting systems that require high reliability. INDEX TERMS Energy harvesting, overcharging protection, SIMO converter, cold start, power-on-reset.
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