This paper describes a new concept for low power consumption TFT-LCDs, based on monolithic multi-drivers. The multi-driver architecture consists of two data line drivers, one analogue, one binary, that can operate in tandem or independently. The analogue driver allows the display to show high quality full colour video images. The binary driver provides 8 colour text data display, either on its own, or superimposed onto the image provided by the analogue driver. Operation of the binary driver consumes 1/10 th of the power that operation of the analogue driver needs. The display module can therefore operate at substantially lower power for many display applications, yet still achieve high display performance when demanded.
Much work has been undertaken to demonstrate the advantages of analogue V U 1 for implementing neural architectures. This paper attempts to address the issues concerning 'in-situ' learning with analogue V U 1 multi-layer perceptron ( M U ) networks. In particular, we propose that 'chip-in-the-loop' learning is, at the very least, necessary to overcome typical analogue process variations and we argue that MLPs containing analogue circuits with 8 bit precision can be successfully trained provided they have digital representations of the weights of at least 12 bits. We demonstrate that weight perturbation, with careful choice of the perturbation size, gives improved results over backpropagation, at the cost of increased training time. Indeed, we go on to show why weight perturbation is possibly the only sensible way to implement MLP 'on-chip' learning.We have designed a set of analogue V U I chips specifically to see ifour theoretical results on learning work in practice.Although these chips are experimental, it is our intention to use them to solve 'real world' problems which have relatively low input dimensionality, such as the task of speaker identijication.
This paper describes an advanced digital display that we have developed for future mobile applications. The 2" QVGA LCD display contains multi-format digital drivers integrated with a low-temperature Continuous Grain Silicon TFT process. These drivers automatically configure the display format based on the contents of the image data that is transmitted to the panel. This strategy provides an optimum balance between display performance and power consumption.
There has been a rapid increase in the resolution of small-sized and medium-sized displays. This study determines an upper discernible limit for display resolution. A range of resolutions varying from 254-1016 PPI were evaluated using simulated display by 49 subjects at 300 mm viewing distance. The results of the study conclusively show that users can discriminate between 339 and 508 PPI and in many cases between 508 and 1016 PPI.
A key requirement for the development of advanced digital drivers for Low Temperature Poly-Silicon (LTPS) active matrix displays is the provision of a high bandwidth, high resolution Digital to Analogue Converter (DAC) as a prerequisite for higher level integration. For a given panel specification and data rate, the bandwidth and resolution of the conversion process directly influence the efficiency of a digital driver implementation in terms of bezel size, transistor count and power consumption. This paper is concerned with the design and realization of a programmable high performance DAC architecture which meets the requirements for a compact and highly efficient digital data driver. The high performance of the two-stage architecture is achieved by means of a novel pre-charge arrangement that not only increases the speed of operation, but also provides for offset compensation of an analogue buffer with considerably reduced slew rate requirements and power consumption. A switched capacitor implementation of the DAC architecture is presented and the theoretical specifications are verified by simulation. The application of the new architecture to advanced digital drivers with programmable input data resolution is briefly discussed.
Results from simulations of weight perturbation as an on-chip learning scheme for analogue VLSI neural networks are presented. The limitations of analogue hardware are modelled as realistically as possible. Thus synaptic weight precision is defined according to the smallest change in the weight setting voltage which gives a measurable change at the output of the corresponding neuron. Tests are carried out on a hard classification problem constructed from mobile robot navigation data. The simulations show that the degradation in classification performance on a 500-pattern test set caused by the introduction of realistic hardware constraints is acceptable: with 8-bit weights, updated probabilistically and with a simplified output error criterion, the error rate increases by no more than 7% when compared with weight perturbation implemented with full 32-bit precision.
Microelectronic neural network technology has become sufficiently mature over the past few years that reliable performance can now be obtained from VLSI circuits under carefully controlled conditions (see Refs. 8 or 13 for example). The use of analogue VLSI allows low power, area efficient hardware realisations which can perform the computationally intensive feed-forward operation of neural networks at high speed, making real-time applications possible. In this paper we focus on important issues for the successful operation and implementation of on-chip learning with such analogue VLSI neural hardware, in particular the issue of weight precision. We first review several perturbation techniques which have been proposed to train multi-layer perceptron (MLP) networks. We then present a novel error criterion which performs well on benchmark problems and which allows simple integration of error measurement hardware for complete on-chip learning systems.
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