9.2: Multi‐Format Digital Display with Content Driven Display Format

Cairns, Graham; Dachs, Catherine; Brownlow, Michael; Kubota, Yasushi; Washio, Hajime; Hijikigawa, Masaya

doi:10.1889/1.1831733

Cited by 10 publications

(7 citation statements)

References 4 publications

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“…Source-driver architecture Figure 2 illustrates the block diagram of the source-driver. The two main function blocks each comprise an R-S shift register [3], [4] and associated transfer gates which generate timing pulses to control, via level shifters, the sampling of the analog video signals onto alternate source lines. In order to reduce the amount of circuitry which is clocked, and therefore minimize power consumption, each function block can be selectively enabled or disabled according to the required resolution.…”

Section: Lcd Controllermentioning

confidence: 99%

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22.2: Multi‐Resolution for Low Power Mobile AMLCD

Maeda¹,

Tsujino²,

Takahasi³

et al. 2002

Symp Digest of Tech Papers

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This paper describes a highly versatile "System LCD" which has been developed for mobile applications. A key feature of the display is a multi-format capability to enable both the color depth and the spatial resolution to be dynamically controlled according to the application. This advanced functionality is realized by integrating a novel source-driver, binary-driver and clock-generator onto the panel. A 3.7" LCD with three principal display formats has been successfully fabricated using low temperature CG-Silicon technology. The power consumption in each format has been measured at 14mW for VGA 8mW for QVGA/Full-color and 2mW for QVGA/Monochrome. We believe this versatile display technology, which combines both high performance and low power consumption, will be essential for the next generation of mobile products. a) Full-color VGA b) Full-color QVGA Figure 5: Photographs of fabricated 3.7" panel SID 02 DIGEST • 797

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Section: Lcd Controllermentioning

confidence: 99%

“…In this paper, we describe Multi-Resolution System-LCDs, based on CG-Silicon technology [1][2] and the Multi-Driver architecture [3] [4]. The LCD modules exhibit high performance with low power consumption, together with high versatility and flexibility.…”

Section: Introductionmentioning

confidence: 99%

22.2: Multi‐Resolution for Low Power Mobile AMLCD

Maeda¹,

Tsujino²,

Takahasi³

et al. 2002

Symp Digest of Tech Papers

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“…The drive capability of standard DAC architectures is only sufficient to drive columns which are local to the DAC circuit, which implies that the digital storage cannot be multiplexed without re-ordering the input data and thereby complicating the interface. If the conversion speed is comparable to the data period then it is attractive to consider a highly multiplexed architecture 4 , requiring a small number of very high-speed DACs with high drive capability as illustrated in Figure 3. The digital input data is sampled and stored locally, prior to conversion into a small number of analogue video phases, which are distributed across the panel.…”

Section: Improving Dac Performance: Simplifying the Digital Drivermentioning

confidence: 99%

“…This is a key innovation for multi-format displays, since the power consumption of the converter can be optimized according to the resolution of the input data 4 . Three different conversion modes can be selected by means of the resolution control signals, 3B and 1B.…”

Section: Principle Of Operationmentioning

confidence: 99%

<title>6-bit multiresolution digital-to-analog converter for low-temperature polysilicon digital drivers</title>

Brownlow

Cairns

Dachs

et al. 2001

Flat Panel Display Technology and Display Metrology II

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A key requirement for the development of advanced digital drivers for Low Temperature Poly-Silicon (LTPS) active matrix displays is the provision of a high bandwidth, high resolution Digital to Analogue Converter (DAC) as a prerequisite for higher level integration. For a given panel specification and data rate, the bandwidth and resolution of the conversion process directly influence the efficiency of a digital driver implementation in terms of bezel size, transistor count and power consumption. This paper is concerned with the design and realization of a programmable high performance DAC architecture which meets the requirements for a compact and highly efficient digital data driver. The high performance of the two-stage architecture is achieved by means of a novel pre-charge arrangement that not only increases the speed of operation, but also provides for offset compensation of an analogue buffer with considerably reduced slew rate requirements and power consumption. A switched capacitor implementation of the DAC architecture is presented and the theoretical specifications are verified by simulation. The application of the new architecture to advanced digital drivers with programmable input data resolution is briefly discussed.

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“…Advanced technologies such as Sharp's CG-Silicon technology [1] [2] have enabled designers to aggressively target low power consumption, small bezel size, high brightness and high display resolution. New monolithic technologies including multi-driver systems [3] [4], multi-resolution drivers [5] and low power non-linear DAC architectures [6] have been developed to target these requirements. Looking forwards, it is recognized that added sensor functionality will be a central feature of next generation LCDs.…”

Section: Introductionmentioning

confidence: 99%