Implementation issues for on-chip learning with analogue VLSI MLPS

Cairns, Graham; Tarassenko, Lionel

doi:10.1049/cp:19950601

Cited by 6 publications

(3 citation statements)

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“…2. With Equation (18) or (19), find the slope factors n * that each one of HTSMC n is implementing. In our case, the slope factors are n * 1 = 2.2845 for HTSMC 2 and n * 2 = 3.8711 for HTSMC 3 .…”

Section: Obtaining Arbitrary Slopesmentioning

confidence: 99%

“…This time, AHTPC s with = 1 and = 0.66 is used to implement an approximation to the function tanh(0.7915x) to deal with the extra slope obtained with the two HTSMC n . The slopes of the target functions are the result of multiplying the theoretical slopes s of AHTPC s by the slope multiplier factors n * of each HTSMC n (see Figure 5 and Equations (18) and (19) for the implemented slope multiplier factors n * as a function of ). Table I includes a detailed list of the slopes of both types of functions and the errors obtained with the simulations depicted in Figure 9.…”

Section: Obtaining Arbitrary Slopesmentioning

confidence: 99%

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Accurate differential tanh(nx) implementation

Carrasco-Robles

Serrano

2008

Circuit Theory & Apps

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SUMMARYThis paper presents a novel non-linear neural activation function architecture that approximates the tanh(nx) function accurately. The purpose of this realization is the description of a circuit that can be designed to obtain different slopes at the origin of the activation function. The special features of transistors working in the subthreshold region are combined with current mode techniques in order to minimize power consumption and occupied area. Moreover, the circuit has been designed with fully differential and balanced topologies so that the external influences, offset, and distortion of even order are reduced. The proposed activation function is thoroughly explained and it is analysed taking the body effect into account. Some modifications are applied in order to immunize it from the body effect, and simulated results for an implementation on a 0.35 m AMI technology are presented.

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Section: Obtaining Arbitrary Slopesmentioning

confidence: 99%

Section: Obtaining Arbitrary Slopesmentioning

confidence: 99%

Accurate differential tanh(nx) implementation

Carrasco-Robles

Serrano

2008

Circuit Theory & Apps

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“…Many digital-or analog-implemented circuits for perceptron have been proposed in the literature, showing good results in the simulation phase [5][6][7][8], however the drawback of these works is the lack of silicon measurement results, which are of a great importance for the investigation of the fundamental characteristics of a perceptron circuit. Besides, the multi-layer perceptron (MLP) is constituted by perceptron, which is a fundamental structure for the feedforward neural network (NN), in VLSI (very-large-scale integration) implementations incorporating various learning algorithms, thus making MLP a common choice as it has been continuously researched for many years [9][10][11][12][13][14]. In the state-of-the-art works, the authors in [15] implement a low-latency MLP processor for real-time cancer detection using field programmable gate arrays (FPGAs), under mass-spectrometry benchmarks, it outperforms both the central processing unit (CPU) and graphics processing unit (GPU) implementations, with an average speedup of 144× and 21×, respectively.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks

Geng

Sun

Nakatake

2020

Sensors

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Perceptron is an essential element in neural network (NN)-based machine learning, however, the effectiveness of various implementations by circuits is rarely demonstrated from chip testing. This paper presents the measured silicon results for the analog perceptron circuits fabricated in a 0.6 μm/±2.5 V complementary metal oxide semiconductor (CMOS) process, which are comprised of digital-to-analog converter (DAC)-based multipliers and phase shifters. The results from the measurement convinces us that our implementation attains the correct function and good performance. Furthermore, we propose the multi-layer perceptron (MLP) by utilizing analog perceptron where the structure and neurons as well as weights can be flexibly configured. The example given is to design a 2-3-4 MLP circuit with rectified linear unit (ReLU) activation, which consists of 2 input neurons, 3 hidden neurons, and 4 output neurons. Its experimental case shows that the simulated performance achieves a power dissipation of 200 mW, a range of working frequency from 0 to 1 MHz, and an error ratio within 12.7%. Finally, to demonstrate the feasibility and effectiveness of our analog perceptron for configuring a MLP, seven more analog-based MLPs designed with the same approach are used to analyze the simulation results with respect to various specifications, in which two cases are used to compare to their digital counterparts with the same structures.

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