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This third-generation chip-multithreading (CMT) SPARC processor is targeted for high-performance servers, and is optimized for both single-and multi-threaded applications. The architecture highlights are provided in [1], while this paper focuses on the physical implementation aspects, providing an overview of circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead. The 396mm 2 chip, shown in Fig. 4.2.1, is fabricated in a 11M 65nm CMOS process and operates at a nominal frequency of 2.3GHz, consuming a maximum power of 250W at 1.2V. Power-management techniques include clock gating at corecluster level and power throttling through a single-thread-issue mode of operation. This mode is used in power-constrained systems without sacrificing single-thread performance.The chip floorplan is symmetrical with the 4 core clusters placed at the corners of the chip and the shared L2-cache crossbar switch in the middle, as shown in Fig. 4.2.1. The SerDes I/O interface occupies three of the chip sides. Process variability and high leakage call for extensive use of static CMOS circuits to improve circuit robustness, minimizing design effort and design time while achieving timing and area targets. Standard-and customcell libraries adhere to common library template rules to facilitate block composition through standard place-and-route tools. Dynamic circuits are limited to high-speed flip-flops and SRAM blocks.The data cache has double the read bandwidth compared to other arrays. The split-wordline cell, shown in Fig. 4.2.2, combined with a single-ended sensing scheme eliminates the potentially marginal self-timed circuits and 2× area overhead of dual-portcell or double-pumped circuit implementations. All arrays use a special bitline-precharge and keeper cell that completes by abutment the edge memory row structure. This reduces the 16-row memory array overhead to 20%, instead of the typical 35%. Clock gating of the non-active portions of the array reduces the overall power. During the write operation both wordlines are turned on, and the complementary data inputs are applied to the bitlines as in a traditional single port cell design. During the read operation however, the single-ended scheme allows the separate use of the two wordlines and bitlines to perform a dual-port style read, as shown in Fig. 4.2.3.The L2 data array operates at the core supply voltage and has a 2-CPU-cycle latency. A single read is performed every 2 cycles and each write operation includes a read of the old data before overwriting with the new data as required by the ECC architecture implementation. The read-before-write operation at the same address occurs without a precharge cycle in between. Several optimization techniques help reduce the area overhead and meet the timing constraints in the L2 cache array. The I/O circuitry, including sense amplifiers, write drivers and output-data latch, are shared by two 128×128b arrays. The column muxes for the top and ...

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