M7: Oracle's Next-Generation Sparc Processor

Aingaran, K.; Jairath, Sumti; Konstadinidis, Georgios; Leung, Serena B.; Loewenstein, Paul; McAllister, Curtis; Phillips, Stephen; Radović, Z.; Sivaramakrishnan, Ram; Smentek, David; Wicki, Thomas

doi:10.1109/mm.2015.35

Cited by 32 publications

(15 citation statements)

References 7 publications

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“…The communications traffic inside the chip itself again can only be larger still. That same recent processor chip [30], for example, has an on-chip network supporting more than 4Tb/s of bisection bandwidth 3 , and the total bandwidth in and out of the "level 3" (L3) cache memory on the chip is 12.8 Tb/s. We part to the other; usually, this will refer to the largest possible number we would find from any such division into two parts.…”

Section: Operationmentioning

confidence: 99%

“…Note any approach that increases the electromagnetic energy concentration while reducing the device active volume by the same factor will reduce the operating energy for such devices. That increased electromagnetic energy density can be from resonators, from slower group velocity (which necessarily requires energy storage somewhere 30 ), or reduced waveguide with F P ≅ 0.477γ. Note that Q is the finesse F multiplied by the cavity length in half-wavelengths.…”

Section: Optical Concentration Factormentioning

confidence: 99%

“…5 (a) shows the neglecting minor possible effects on these from this waveguide structure with a wavelength-scale cross-section. 29 Formally, a conventional laser cannot run with such a structure because there is no resonator, but we can equivalently presume a hypothetical device that is about one "gain" length long, i.e., a gain of a factor of e. 30 After a pulse enters a structure, its energy has to be stored inside the structure somewhere until it exits the structure again. Unless we have some "side" resonator or other energy store, the energy will be stored as electromagnetic energy inside the material.…”

Section: Optical Concentration Factormentioning

confidence: 99%

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Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Miller

2017

J. Lightwave Technol.

570

406

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Optics offers unique opportunities for reducing energy in information processing and communications while simultaneously resolving the problem of interconnect bandwidth density inside machines. Such energy dissipation overall is now at environmentally significant levels; the source of that dissipation is progressively shifting from logic operations to interconnect energies. Without the prospect of substantial reduction in energy per bit communicated, we cannot continue the exponential growth of our use of information. The physics of optics and optoelectronics fundamentally addresses both interconnect energy and bandwidth density, and optics may be the only scalable solution to such problems. Here we summarize the corresponding background, status, opportunities, and research directions for optoelectronic technology and novel optics, including sub-femtojoule devices in waveguide and novel 2D array optical systems. We compare different approaches to low-energy optoelectronic output devices and their scaling, including lasers, modulators and LEDs, optical confinement approaches (such as resonators) to enhance effects, and the benefits of different material choices, including 2D materials and other quantum-confined structures. With such optoelectronic energy reductions, and the elimination of line charging dissipation by the use optical connections, the next major interconnect dissipations are in the electronic circuits for receiver amplifiers, timing recovery and multiplexing. We show we can address these through the integration of photodetectors to reduce or eliminate receiver circuit energies, free-space optics to eliminate the need for timing and multiplexing circuits (while also solving bandwidth density problems), and using optics generally to save power by running large synchronous systems. One target concept is interconnects from ~ 1 cm to ~ 10 m that have the same energy (~ 10fJ/bit) and simplicity as local electrical wires on chip.

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Section: Operationmentioning

confidence: 99%

Section: Optical Concentration Factormentioning

confidence: 99%

Section: Optical Concentration Factormentioning

confidence: 99%

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Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Miller

2017

J. Lightwave Technol.

570

406

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“…Future work with performance portability frameworks like Kokkos [21] will explore how much must be exposed to programmers. Another approach is to push memory-centric aspects to an accelerator like Sparc M7's data analytics accelerator [22] for database operations or Graphicionado [23] for graph analysis.…”

Section: Related Workmentioning

confidence: 99%

A microbenchmark characterization of the Emu chick

Young

Hein²,

Eswar

et al. 2019

Parallel Computing

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The Emu Chick is a prototype system designed around the concept of migratory memory-side processing. Rather than transferring large amounts of data across power-hungry, high-latency interconnects, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each memory read. The current prototype hardware uses FPGAs to implement cache-less "Gossamer" cores for computational work and rely on a typical stationary core (PowerPC) to run basic operating system functions and migrate threads between nodes. In this multi-node characterization of the Emu Chick, we extend an earlier single-node investigation [1] of the the memory bandwidth characteristics of the system through benchmarks like STREAM, pointer chasing, and sparse matrix-vector multiplication. We compare the Emu Chick hardware to architectural simulation and an Intel Xeon-based platform. Our results demonstrate that for many basic operations the Emu Chick can use available memory bandwidth more efficiently than a more traditional, cache-based architecture although bandwidth usage suffers for computationally intensive workloads like SpMV. Moreover, the Emu Chick provides stable, predictable performance with up to 65% of the peak bandwidth utilization on a random-access pointer chasing benchmark with weak locality.

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“…The shift from 32-bit to 64-bit architectures enables 16 exabytes of memory to be addressable, a number which significantly exceeds the amount of memory needed for applications targeting these architectures. This fact motivated the support for tagged pointers in modern commodity architectures: AArch64 with 8-bit pointer tags [34] and Sparc M7 with up to 32-bit pointer tags [35].…”

Section: A Pointer Taggingmentioning

confidence: 99%

MaxSim: A simulation platform for managed applications

Rodchenko

Kotselidis

Nisbet

et al. 2017

2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Managed applications, written in programming languages such as Java, C# and others, represent a significant share of workloads in the mobile, desktop, and server domains. Microarchitectural timing simulation of such workloads is useful for characterization and performance analysis, of both hardware and software, as well as for research and development of novel hardware extensions. This paper introduces MaxSim, a simulation platform based on the Maxine VM, the ZSim simulator, and the McPAT modeling framework. MaxSim is able to simulate fast and accurately managed workloads running on top of Maxine VM and its capabilities are showcased with novel simulation techniques for: 1) low-intrusive microarchitectural profiling via pointer tagging on the x86-64 platforms, 2) modeling of hardware extensions related, but not limited to, tagged pointers, and 3) modeling of complex software changes via address-space morphing. Low-intrusive microarchitectural profiling is achieved by utilizing tagged pointers to collect type-and allocation-site-related hardware events. Furthermore, MaxSim allows, through a novel technique called address space morphing, the easy modeling of complex object layout transformations. Finally, through the codesigned capabilities of MaxSim, novel hardware extensions can be implemented and evaluated. We showcase MaxSim's capabilities by simulating the whole set of the DaCapo-9.12-bach benchmarks in less than a day while performing an up-to-date microarchitectural power and performance characterization. Furthermore, we demonstrate a hardware/software co-designed optimization that performs dynamic load elimination for array length retrieval achieving up to 14% L1 data cache loads reduction and up to 4% dynamic energy reduction. MaxSim is available at https://github.com/arodchen/ MaxSim released as free software.

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M7: Oracle's Next-Generation Sparc Processor

Cited by 32 publications

References 7 publications

Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Attojoule Optoelectronics for Low-Energy Information Processing and Communications

A microbenchmark characterization of the Emu chick

MaxSim: A simulation platform for managed applications

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