The Next Generation 64b SPARC Core in a T4 SoC Processor

Shin, Jinuk Luke; Golla, Robert; Li, Hongping; Dash, Sudesna; Choi, Yong‐Jin; Smith, Alan; Sathianathan, H.; Joshi, Manjunath V.; Park, Heechoul; Elgebaly, M.; Turullols, Sebastian; Kim, Song; Masleid, Robert P.; Konstadinidis, Georgios; Doherty, Mary Jo; Grohoski, Greg; McAllister, Curtis

doi:10.1109/jssc.2012.2223036

Cited by 39 publications

(13 citation statements)

References 8 publications

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“…We evaluate BuMP in the context of a lean-core CMP with 16 cores, a modestly sized last-level cache, and a crossbar-based NOC that minimizes the delay to the LLC. Prior research has shown that large LLC capacities are counter-productive for server workloads and that a fast path to the LLC is critical to server processor performance [9,10,32,43]. The chip is modelled in 22nm technology with high-performance process for all the components except the LLC which uses low-leakage process.…”

Section: A Methodologymentioning

confidence: 99%

BuMP: Bulk Memory Access Prediction and Streaming

Volos¹,

Picorel²,

Falsafi³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As the industry moves to lean-core server processors, the energy bottleneck is shifting toward main memory as a chief source of server energy consumption in modern datacenters. Maximizing the energy efficiency of today's DRAM chips and interfaces requires amortizing the costly DRAM page activations over multiple row buffer accesses.This work introduces Bulk Memory Access Prediction and Streaming, or BuMP. We make the observation that a significant fraction (59-79%) of all memory accesses fall into DRAM pages with high access density, meaning that the majority of their cache blocks will be accessed within a modest time frame of the first access. Accesses to high-density DRAM pages include not only memory reads in response to load instructions, but also reads stemming from store instructions as well as memory writes upon a dirty LLC eviction. The remaining accesses go to low-density pages and virtually unpredictable reference patterns (e.g., hashed key lookups). BuMP employs a low-cost predictor to identify high-density pages and triggers bulk transfer operations upon the first read or write to the page. In doing so, BuMP enforces high row buffer locality where it is profitable, thereby reducing DRAM energy per access by 23%, and improves server throughput by 11% across a wide range of server applications.

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Section: A Methodologymentioning

confidence: 99%

BuMP: Bulk Memory Access Prediction and Streaming

Volos¹,

Picorel²,

Falsafi³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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“…Using a modified version of CACTI 5. 3 [24], we model a 128-entry × 64 b two-read/one-write ported RF and the breakdown of dynamic power and leakage power of RF components is shown in Fig. 2.…”

Section: A Motivational Examplementioning

confidence: 99%

“…A S A fundamental part in modern microprocessors, register file (RF) enhances the performance by shrinking the performance gap between microprocessor and memory systems, as well as increasing instruction level parallelism through implementing register renaming [1]- [3]. However, with aggressive technology scaling, power efficiency and reliability have become two main challenges to RF designers.…”

Section: Introductionmentioning

confidence: 99%

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Gong

Wang

Jiang

et al. 2015

IEEE Trans. VLSI Syst.

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Modern microprocessors employ register files (RFs) for performance enhancement and achieving instruction level parallelism simultaneously. However, RF incurs large power consumption owing to the highly frequent access. Meanwhile, as technology scales, bias temperature instability has become a major reliability concern for RF designers. This paper presents an aging-aware trimodal register file (TM-RF) design to enhance the power efficiency. As instructions pass through the pipeline, TM-RF places the bit-cells in different modes based on the register activity, thereby achieving significant power reduction. To meet design constraints of different applications, we present four schemes to implement the proposed design, providing design flexibility. Additionally, with device selection and worst case sizing methodology, we mitigate aging-effect-induced RF reliability degradation. Simulation results on SPEC 2000 benchmarks demonstrate that TM-RF achieves up to 81.4% power savings and 17% reliability improvement on average, with minimal impact on performance.Index Terms-Leakage current, low power, bias temperature instability (NBTI/PBTI), process variation, register file (RF). 1063-8210

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“…transaction processing [41], data/control-plane processing [20] and the embedded space [16]. While direct comparisons between in-order and OOO designs are difficult, OOO designs seem to consistently provide higher single-thread performance relative to comparably provisioned inorder designs [22].…”

Section: The Perceived Out-of-order Performance Advantagementioning

confidence: 99%

Discerning the dominant out-of-order performance advantage

McFarlin¹,

Tucker

Zilles

2013

Proceedings of the Eighteenth International Conference on Architectural Support for Programming Languages and Operating Systems

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In this paper, we set out to study the performance advantages of an Out-of-Order (OOO) processor relative to in-order processors with similar execution resources. In particular, we try to tease apart the performance contributions from two sources: the improved schedules enabled by OOO hardware speculation support and its ability to generate different schedules on different occurrences of the same instructions based on operand and functional unit availability. We find that the ability to express good static schedules achieves the bulk of the speedup resulting from OOO. Specifically, of the 53% speedup achieved by OOO relative to a similarly provisioned inorder machine, we find that 88% of that speedup can be achieved by using a single "best" static schedule as suggested by observing an OOO schedule of the code. We discuss the ISA mechanisms that would be required to express these static schedules.Furthermore, we find that the benefits of dynamism largely come from two kinds of events that influence the application's critical path: load instructions that miss in the cache only part of the time and branch mispredictions. We find that much of the benefit of OOO dynamism can be achieved by the potentially simpler task of addressing these two behaviors directly.

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The Next Generation 64b SPARC Core in a T4 SoC Processor

Cited by 39 publications

References 8 publications

BuMP: Bulk Memory Access Prediction and Streaming

BuMP: Bulk Memory Access Prediction and Streaming

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Discerning the dominant out-of-order performance advantage

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