4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor

Li, Penny; Shin, Jinuk Luke; Konstadinidis, Georgios; Schumacher, Francis; Krishnaswamy, V.; Cho, Hoyeol; Dash, Sudesna; Masleid, Robert P.; Zheng, Chaoyang; Lin, Yuanjung David; Loewenstein, Paul; Park, Heechoul; Srinivasan, Vijay; Huang, Dawei; Hwang, Chul Ju; Hsu, W.-J.; McAllister, Curtis

doi:10.1109/isscc.2015.7062931

Cited by 10 publications

(6 citation statements)

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“…Adding this to the fact that latency bottlenecks (both due to fetching instructions from the L3 cache, and fetching data from main memory) are still far from eliminated suggests potential for wider SMT: with more threads per core, as seen in some server chips [30]. This case is strengthened by the low memory bandwidth utilization shown earlier -even with more threads per core bandwidth is unlikely to become a bottleneck.…”

Section: Simultaneous Multi-threadingmentioning

confidence: 98%

Profiling a warehouse-scale computer

Kanev

Darago

Hazelwood

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

287

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With the increasing prevalence of warehouse-scale (WSC) and cloud computing, understanding the interactions of server applications with the underlying microarchitecture becomes ever more important in order to extract maximum performance out of server hardware. To aid such understanding, this paper presents a detailed microarchitectural analysis of live datacenter jobs, measured on more than 20,000 Google machines over a three year period, and comprising thousands of different applications.We first find that WSC workloads are extremely diverse, breeding the need for architectures that can tolerate application variability without performance loss. However, some patterns emerge, offering opportunities for co-optimization of hardware and software. For example, we identify common building blocks in the lower levels of the software stack. This "datacenter tax" can comprise nearly 30% of cycles across jobs running in the fleet, which makes its constituents prime candidates for hardware specialization in future server systems-on-chips. We also uncover opportunities for classic microarchitectural optimizations for server processors, especially in the cache hierarchy. Typical workloads place significant stress on instruction caches and prefer memory latency over bandwidth. They also stall cores often, but compute heavily in bursts. These observations motivate several interesting directions for future warehouse-scale computers.

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Section: Simultaneous Multi-threadingmentioning

confidence: 98%

Profiling a warehouse-scale computer

Kanev

Darago

Hazelwood

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

287

View full text Add to dashboard Cite

show abstract

“…Note however, that, even after we account for 2-wide SMT, 75% of collected fleet samples show an IPC value of 1.2 or less (last plot of Figure 14), compared to a theoretical machine width of 4.0. Adding this to the fact that latency bottlenecks (both due to fetching instructions from the L3 cache, and fetching data from main memory) are still far from eliminated suggests potential for wider SMT: with more threads per core, as seen in some server chips [30]. This case is strengthened by the low memory bandwidth utilization shown earlier -even with more threads per core bandwidth is unlikely to become a bottleneck.…”

Section: Simultaneous Multi-threadingmentioning

confidence: 98%

“…For example, the snappy algorithm was designed specifically to achieve higher (de)compression speeds than gzip, sacrificing compression ratios in the process. Its usage might decrease in the presence of sufficiently fast hardware for better-compressing algorithms [30,39].…”

Section: Datacenter Taxmentioning

confidence: 99%

“…While partitioning has been extensively studied for multiple applications' access streams in shared last-level caches (Qureshi and Patt [43], among many others), relatively little attention has been paid to treating the instruction and data streams differently, especially in private, mid-level caches. Recently, Jaleel et al proposed modifying replacement policies to prioritize code over data [21], and the SPARC M7 design team opted for an architecture with completely separate L2 instruction and data caches [30].…”

Section: Instruction Cache Bottlenecksmentioning

confidence: 99%

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Profiling a warehouse-scale computer

Kanev

Darago

Hazelwood

et al. 2015

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

With the increasing prevalence of warehouse-scale (WSC) and cloud computing, understanding the interactions of server applications with the underlying microarchitecture becomes ever more important in order to extract maximum performance out of server hardware. To aid such understanding, this paper presents a detailed microarchitectural analysis of live datacenter jobs, measured on more than 20,000 Google machines over a three year period, and comprising thousands of different applications. We first find that WSC workloads are extremely diverse, breeding the need for architectures that can tolerate application variability without performance loss. However, some patterns emerge, offering opportunities for co-optimization of hardware and software. For example, we identify common building blocks in the lower levels of the software stack. This "datacenter tax" can comprise nearly 30% of cycles across jobs running in the fleet, which makes its constituents prime candidates for hardware specialization in future server systems-on-chips. We also uncover opportunities for classic microarchitectural optimizations for server processors, especially in the cache hierarchy. Typical workloads place significant stress on instruction caches and prefer memory latency over bandwidth. They also stall cores often, but compute heavily in bursts. These observations motivate several interesting directions for future warehouse-scale computers.

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“…One thread is accelerators for data analytics. Accelerator designs have been proposed for query procssing bottlenecks [11,28,35,38,41,50,55,56]. Researchers have explored customized accelerators for common operators in SQL such as join [56], partition [11,55,56], sort [56], aggregation [56], regex search [28,50,56], and index traversal [38].…”

Section: Discussion and Related Workmentioning

confidence: 99%

Accelerating raw data analysis with the ACCORDA software and hardware architecture

2019

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The data science revolution and growing popularity of data lakes make efficient processing of raw data increasingly important. To address this, we propose the ACCelerated Operators for Raw Data Analysis (ACCORDA) architecture. By extending the operator interface (subtype with encoding) and employing a uniform runtime worker model, ACCORDA integrates data transformation acceleration seamlessly, enabling a new class of encoding optimizations and robust high-performance raw data processing. Together, these key features preserve the software system architecture, empowering state-of-art heuristic optimizations to drive flexible data encoding for performance. ACCORDA derives performance from its software architecture, but depends critically on the acceleration of the Unstructured Data Processor (UDP) that is integrated into the memory-hierarchy, and accelerates data transformation tasks by 16x-21x (parsing, decompression) to as much as 160x (deserialization) compared to an x86 core. We evaluate ACCORDA using TPC-H queries on tabular data formats, exercising raw data properties such as parsing and data conversion. The ACCORDA system achieves 2.9x-13.2x speedups when compared to SparkSQL, reducing raw data processing overhead to a geomean of 1.2x (20%). In doing so, ACCORDA robustly matches or outperforms prior systems that depend on caching loaded data, while computing on raw, unloaded data. This performance benefit is robust across format complexity, query predicates, and selectivity (data statistics). ACCORDA's encoding-extended operator interface unlocks aggressive encoding-oriented optimizations that deliver 80% average performance increase over the 7 affected TPC-H queries.

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4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor

Cited by 10 publications

References 1 publication

Profiling a warehouse-scale computer

Profiling a warehouse-scale computer

Profiling a warehouse-scale computer

Accelerating raw data analysis with the ACCORDA software and hardware architecture

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