I. AbstractA high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 µA/um and 1259 µA/um respectively, at an off-current of 200 nA/um (V dd =1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 µm 2 . II. Technology DescriptionThe major ground rules used in this technology are equivalent to our 65-nm-baseline technology which utilizes DSL for enhanced performance [1]. DSL is a process integration flow that combines tensile and compressive stress silicon nitride liners on nFET and pFET devices respectively, resulting in increased channel strain and performance for both. Fig. 1 shows our baseline flow with additional enhanced strain process steps. Specifically, the embedded SiGe process is implemented with epitaxial SiGe growth in cavities etched into the source/drain areas of the pFETs. The nFETs are covered with a nitride hardmask during recess etch and epitaxial growth of SiGe in the pFET areas. Photolithography is utilized to mask the nFET areas while the hardmask is etched into a spacer in the pFET areas. This spacer defines the proximity of the SiGe to the channel area and prevents SiGe growth on the pFET polysilicon gate electrode. A stress memorization technique (SMT) is implemented for the nFETs where increased tensile strain was achieved by the deposition of a stress dielectric film and subsequent thermal anneal.The remaining process flow steps are equivalent to our baseline CMOS process, except for a modified Ni silicide process that achieves improved contact and stability on SiGe. This is followed by DSL implementation in the middle-of-line (MOL) [2]. A cross-sectional TEM image of a completed device is shown in Fig. 2, also shown is an AFM image of the surface morphology of the source/drain area of the pFET demonstrating a smooth RMS roughness value of 0.11 nm. The advanced-low-K dielectric film used in the BEOL interconnect levels is based on the K=2.75 material previously discussed [3]. This film has been optimized for lower permittivity (K=2.75) and stress. Extendibility of the film into both 2x and 4x fatwire levels has been demonstrated. III. FEOL Performance ResultsA plot of the Ion-Ioff characteristics is shown in Fig. 3 along with the transistor characteristics in Fig. 4 at 1.0 V Vdd, where the threshold voltage roll-off is well-behaved down to 30 nm gate length, and sub-threshold swing is maintained at ~110 mV/dec (Fig. 5-6). pFET AC switching on-current of 735 µA/µm at off-current of 200 nA/µm with a corresponding DC on-current of 700 µA/µm was achieved. For the nFET, the AC switching on-current was 1259 µA/µm and the DC on-cur...
Three-dimensional carbon nanotube (CNT) forest microstructures are synthesized using sequenced, site-specific synthesis techniques. Thin-film layers of Al2O3 and Al2O3/Fe are patterned to support film-catalyst and floating-catalyst chemical vapor deposition (CVD) in specific areas. Al2O3 regions support only floating-catalyst CVD, whereas regions of layered Al2O3/Fe support both film- and floating-catalyst CNT growth. Sequenced application of the two CVD methods produced heterogeneous 3D CNT forest microstructures, including regions of only film-catalyst CNTs, only floating-catalyst CNTs, and vertically stacked layers of each. The compressive mechanical behavior of the heterogeneous CNT forests was evaluated, with the stacked layers exhibiting two distinct buckling plateaus. Finite element simulation of the stacked layers demonstrated that the relatively soft film-catalyst CNT forests were nearly fully buckled prior to large-scale deformation of the bottom floating-catalyst CNT forests.
Area-selective atomic layer deposition (AS-ALD) techniques are an emerging class of bottom-up nanofabrication techniques that selectively deposit patterned ALD films without the need for conventional top-down lithography. To achieve this patterning, most reported AS-ALD techniques use a chemical inhibitor layer to proactively block ALD surface reactions in selected areas. Herein, an AS-ALD process is demonstrated that uses a focused electron beam (e-beam) to dissociate ambient water vapor and "write" highly resolved hydroxylated patterns on the surface of highly oriented pyrolytic graphite (HOPG). The patterned hydroxylated regions then support subsequent ALD deposition. The ebeam functionalization technique facilitates precise pattern placement through control of beam position, dwell time, and current. Spatial resolution of the technique exceeded 42 nm, with a surface selectivity of between 69.9% and 99.7%, depending on selection of background nucleation regions. This work provides a fabrication route for AS-ALD on graphitic substrates suitable for fabrication of graphene-based nanoelectronics.
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