Through-wafer electrical connections are becoming increasingly important for three-dimensional integrated circuits, microelectromechanical systems packaging and radio-frequency components. In this paper, we report our current results on the formation of through-wafer metal plugs using the copper electroplating technique. Several approaches for via filling are investigated, such as filling before or after wafer thinning. Among the methods experimented, the one-side Cu plating and bottom-up filling appears to be the most suitable technique for copper filling into high aspect ratio vias. Using this method, we demonstrate the successful filling of vias with an aspect ratio of up to 7. Copper plugs as small as 20 × 20 μm2 are obtained uniformly over 4 inch Si wafers.
Articles you may be interested inFormation of three-dimensional and nanowall structures on silicon using a hydrogen-assisted high aspect ratio etching J.High aspect ratio silicon etch: A review An advanced, time-multiplexed plasma etch process for high aspect ratio structures is presented. Compared to the two pulse Bosch process, the technique consists of a sequence of three pulses. The third pulse is tailored to improved depassivation of the trench bottom prior to each etch pulse. Several depassivation chemistries are explored: O 2 , CO 2 , and SO 2 . In a further extension the bias voltage is also pulsed, with the aim to balance the radical and ion-enhanced components in the passivation of the sidewalls and trench bottom. The process extensions lead to improved mask selectivity and substantial range for profile control from fully anisotropic to strongly negatively tapered. The maximum aspect ratio obtained in the Bosch process could not be improved, because the ion angular distribution probably remains the limiting factor. The role of the ions in passivation and etching has been quantified in separate experiments.
A cryogenic SF6/O2 plasma process has been used to investigate the etching of deep holes in silicon wafers. The influence of crystallographic and aspect ratio dependence of the etch rate on the holes profile have been explored. It was found that wafer temperature, during the etching process, played a crucial role in controlling the anisotropy and deteriorative faceting due to crystal orientation dependent etching. High anisotropy and switching of the process to crystallographic independent etching was achieved by controlling the temperature. Aspect ratio dependent etching was also identified as a serious limitation for the required homogeneity in etched depth.
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