Abstract-In this paper a novel architecture of on-chip clock generation employs a network of oscillators synchronized by a network of all-digital PLLs (ADPLLs). In the implemented prototype 16 local clock generators are synchronized by the ADPLL network, with an output frequency of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs.
Abstract-This paper focuses on clock generation and distribution in large SoC. After a brief analysis of diverse existed approaches, we propose a distributed architecture based on coupled local clock generators. Three prototypes are presented to demonstrate the feasibility of a large globally synchronous SoC with high reliability by using this approach. Moreover, the reconfigurability feature of this architecture provides a platform for exploring topologies with potentially improved performance.
International audienceThis paper presents a CMOS 1.1-2.8 GHz 10 bits digitally controlled oscillator (DCO) for high speed clocking of SoCs. The DCO includes only 269 tuning cells, which is possible thanks to an original algorithm based on weighted combined thermometer code, used for the DCO frequency control. The control circuit of the DCO includes only binary-to-thermometer decoders: that was possible with the proposed technique of virtual extension of number of the DCO ring. It was implemented in 65- nm CMOS technology, with semi-custom layout design allowed to optimize the area on silicon. The design was validated by transistor-level ELDO extracted schematic simulation. Oscillator shows a good linearity in the frequency tunning range, with average power consumption 6mW/GHz with 1.1V supply voltage. Typical phase noise with 1MHz offset and 2GHz carrying frequency is -86.12dBc/Hz
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