A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation

Abstract

International audienceThis paper presents a CMOS 1.1-2.8 GHz 10 bits digitally controlled oscillator (DCO) for high speed clocking of SoCs. The DCO includes only 269 tuning cells, which is possible thanks to an original algorithm based on weighted combined thermometer code, used for the DCO frequency control. The control circuit of the DCO includes only binary-to-thermometer decoders: that was possible with the proposed technique of virtual extension of number of the DCO ring. It was implemented in 65- nm CMOS technology, with semi-custom layout design allowed to optimize the area on silicon. The design was validated by transistor-level ELDO extracted schematic simulation. Oscillator shows a good linearity in the frequency tunning range, with average power consumption 6mW/GHz with 1.1V supply voltage. Typical phase noise with 1MHz offset and 2GHz carrying frequency is -86.12dBc/Hz

A comprehensive in-depth study of tri-state inverter based DCO

“…Then, in this section, for convenience, we focus on the output frequency instead of the oscillation period. As an extra contribution to [16], we provide the theory demonstrating the published simulation results and the measurement results as a proof. Finally, the jitter is analyzed.…”

“…Having said that, Control R is the most widely used strategy, see [9,[14][15][16]. Therefore, the study continues with Circuit-M (M for Measurement) whose tuning strategy relies on Control R .…”

“…One can note that the circuit was fully described in [16] as a DCO featuring a linear transfer characteristic for the output frequency versus the input code. Then, in this section, for convenience, we focus on the output frequency instead of the oscillation period.…”

“…One of the actual trends in tuning the oscillation frequency is based on the association of a classic RO and an array of Tri-State (TS) inverters as illustrated by Fig. 1 [14][15][16]. Complications occur when designing the circuit.…”

Distributed clock generator for synchronous SoC using ADPLL network

“…The implemented DCOs are the ring CMOS oscillators employing width-modulated technique for the digital frequency tuning [6], [7]. Their structure is based on a 7-stage ring oscillator (Fig.…”