Abstract-This paper presents a FPGA platform for the design and study of network of coupled all-digital phase locked loops (ADPLLs), destinated for clock generation in a large synchronous system on chip (SOC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described. The paper emphasises the difference between the FPGA and ASIC-based implementation of such a system, in particular, implementation of digitally contolled oscillators and phase-frequency detector. The FPGA-implemented network allows to study complex phenomena related with coupled ADPLL operation, and to exploit stability issues and nonlinear behaviour. A dynamic setup mechanism has been proposed for the network, allowing to select the desirable synchronised state. Experimental results demonstrate the global synchronization of network and performance of the network for different configuraitons.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.