All-digital PLL array provides reliable distributed clock for SOCs

Javidan, Mohammad Mahdi; Zianbetov, Eldar; Anceau, François; Galayko, D.; Korniienko, Anton; Colinet, Éric; Scorletti, Gérard; Akre, J. M.; Jerome, J. Terrence Jose

doi:10.1109/iscas.2011.5938134

Cited by 15 publications

(20 citation statements)

References 8 publications

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“…Fig. 12 and [6]) and clocking network has the accumulative errors. They increase with the distance from the reference point and introduce an undesired skew.…”

Section: A Desirable Mode Selectionmentioning

confidence: 99%

“…The proposed method is based on an on-fly dynamic reconfiguration of the network [6]. The reconfiguration procedure is performed during the start-up and consists of two steps:…”

Section: A Desirable Mode Selectionmentioning

confidence: 99%

“…1(b), [4] [5]. These areas are also known as isochronous zones [4] or synchronous clocking areas (SCA) [6]. Each zone has its own local clock: The zones are small enough so that the clock distribution inside the zones can easily be achieved by conventional techniques.…”

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confidence: 99%

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A reconfigurable distributed architecture for clock generation in large many-core SoC

Shan

Galayko

Anceau

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-This paper focuses on clock generation and distribution in large SoC. After a brief analysis of diverse existed approaches, we propose a distributed architecture based on coupled local clock generators. Three prototypes are presented to demonstrate the feasibility of a large globally synchronous SoC with high reliability by using this approach. Moreover, the reconfigurability feature of this architecture provides a platform for exploring topologies with potentially improved performance.

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“…Fig. 12 and [6]) and clocking network has the accumulative errors. They increase with the distance from the reference point and introduce an undesired skew.…”

Section: A Desirable Mode Selectionmentioning

confidence: 99%

“…The proposed method is based on an on-fly dynamic reconfiguration of the network [6]. The reconfiguration procedure is performed during the start-up and consists of two steps:…”

Section: A Desirable Mode Selectionmentioning

confidence: 99%

See 1 more Smart Citation

A reconfigurable distributed architecture for clock generation in large many-core SoC

Shan

Galayko

Anceau

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

View full text Add to dashboard Cite

show abstract

“…The proposed method is based on an on-fly dynamic reconfiguration of the network [8]. The reconfiguration procedure is performed during the start-up and consists of two steps:…”

Section: Desirable Mode Selectionmentioning

confidence: 99%

“…This mode excludes the cycles of propagation of information, hence eliminates the possibility of undesired locking. However, in such an operation mode the suppression of perturbations is weak [8] and clocking network has the accumulative errors. They increase with the distance from the reference point and introduce an undesired skew.…”

Section: Desirable Mode Selectionmentioning

confidence: 99%

Distributed clock generator for synchronous SoC using ADPLL network

Zianbetov

Galayko

Anceau

et al. 2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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Abstract-In this paper a novel architecture of on-chip clock generation employs a network of oscillators synchronized by a network of all-digital PLLs (ADPLLs). In the implemented prototype 16 local clock generators are synchronized by the ADPLL network, with an output frequency of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs.

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Synchronization in networks of mutually delay-coupled phase-locked loops

et al. 2014

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Electronic components that perform tasks in a concerted way rely on a common time reference. For instance, parallel computing demands synchronous clocking of multiple cores or processors to reliably carry out joint computations. Here, we show that mutually coupled phase-locked loops (PLLs) enable synchronous clocking in large-scale systems with transmission delays. We present a phase description of coupled PLLs that includes filter kernels and delayed signal transmission. We find that transmission delays in the coupling enable the existence of stable synchronized states, while instantaneously coupled PLLs do not tend to synchronize. We show how filtering and transmission delays govern the collective frequency and the time scale of synchronization. chips, mobile communication systems, and antenna arrays [1][2][3][4]. Parallel processing requires coordination of the different components. In multi-core systems, for instance, the trend to integrate more and more processing cores in a single silicon die is driven by benefits in computational performance, energy and cost efficiency. Such systems may consist of tens to hundreds of cores. One important strategy to coordinate the components is to provide a common time reference using clocking devices. Global coordination can be achieved using a master-clock design, where one master clock synchronizes different cores via a so-called clock tree using phase-locked loops (figure 1). A phase-locked loop (PLL) generates a clock signal controlled by an external master clock using internal feedback [5,6]. This clocking design is efficient for small systems but becomes space and energy inefficient as system size increases [7,8]. Therefore, the standard method to provide clocking for large systems with many cores is the so-called globally asynchronous locally synchronous (GALS) clocking [9]. In this approach, only local subgroups of components are in synchrony, while communication between asynchronous subgroups requires waiting cycles to guarantee proper parallel processing. Therefore, this approach leads to performance loss due to communication latencies between domains with different time references [10,11]. For these reasons, it is important to find alternative clocking designs that are optimized to function in large systems.In principle, global coordination of many components could be achieved by self-organized synchronization via mutual coupling. Such an approach does not rely on a master clock and is thus expected to be scalable [12][13][14]. At high clock rates of several gigahertz which are common in modern electronics, significant transmission delays arise on the centimeter scale and influence the system behavior. This raises the question which system architectures are needed to obtain global synchrony in large systems and whether transmission delays pose an extra challenge.In this paper, we derive a phase model for a network of mutually coupled phase-locked loops with transmission delays but without a master clock (figure 1). In section 2, we give a brief introduction to ...

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All-digital PLL array provides reliable distributed clock for SOCs

Cited by 15 publications

References 8 publications

A reconfigurable distributed architecture for clock generation in large many-core SoC

A reconfigurable distributed architecture for clock generation in large many-core SoC

Distributed clock generator for synchronous SoC using ADPLL network

Synchronization in networks of mutually delay-coupled phase-locked loops

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