Electronic components that perform tasks in a concerted way rely on a common time reference. For instance, parallel computing demands synchronous clocking of multiple cores or processors to reliably carry out joint computations. Here, we show that mutually coupled phase-locked loops (PLLs) enable synchronous clocking in large-scale systems with transmission delays. We present a phase description of coupled PLLs that includes filter kernels and delayed signal transmission. We find that transmission delays in the coupling enable the existence of stable synchronized states, while instantaneously coupled PLLs do not tend to synchronize. We show how filtering and transmission delays govern the collective frequency and the time scale of synchronization. chips, mobile communication systems, and antenna arrays [1][2][3][4]. Parallel processing requires coordination of the different components. In multi-core systems, for instance, the trend to integrate more and more processing cores in a single silicon die is driven by benefits in computational performance, energy and cost efficiency. Such systems may consist of tens to hundreds of cores. One important strategy to coordinate the components is to provide a common time reference using clocking devices. Global coordination can be achieved using a master-clock design, where one master clock synchronizes different cores via a so-called clock tree using phase-locked loops (figure 1). A phase-locked loop (PLL) generates a clock signal controlled by an external master clock using internal feedback [5,6]. This clocking design is efficient for small systems but becomes space and energy inefficient as system size increases [7,8]. Therefore, the standard method to provide clocking for large systems with many cores is the so-called globally asynchronous locally synchronous (GALS) clocking [9]. In this approach, only local subgroups of components are in synchrony, while communication between asynchronous subgroups requires waiting cycles to guarantee proper parallel processing. Therefore, this approach leads to performance loss due to communication latencies between domains with different time references [10,11]. For these reasons, it is important to find alternative clocking designs that are optimized to function in large systems.In principle, global coordination of many components could be achieved by self-organized synchronization via mutual coupling. Such an approach does not rely on a master clock and is thus expected to be scalable [12][13][14]. At high clock rates of several gigahertz which are common in modern electronics, significant transmission delays arise on the centimeter scale and influence the system behavior. This raises the question which system architectures are needed to obtain global synchrony in large systems and whether transmission delays pose an extra challenge.In this paper, we derive a phase model for a network of mutually coupled phase-locked loops with transmission delays but without a master clock (figure 1). In section 2, we give a brief introduction to ...
Self-organized synchronization occurs in a variety of natural and technical systems but has so far only attracted limited attention as an engineering principle. In distributed electronic systems, such as antenna arrays and multi-core processors, a common time reference is key to coordinate signal transmission and processing. Here we show how the self-organized synchronization of mutually coupled digital phase-locked loops (DPLLs) can provide robust clocking in large-scale systems. We develop a nonlinear phase description of individual and coupled DPLLs that takes into account filter impulse responses and delayed signal transmission. Our phase model permits analytical expressions for the collective frequencies of synchronized states, the analysis of stability properties and the time scale of synchronization. In particular, we find that signal filtering introduces stability transitions that are not found in systems without filtering. To test our theoretical predictions, we designed and carried out experiments using networks of off-the-shelf DPLL integrated circuitry. We show that the phase model can quantitatively predict the existence, frequency, and stability of synchronized states. Our results demonstrate that mutually delay-coupled DPLLs can provide robust and self-organized synchronous clocking in electronic systems.
This work presents synchronization of two bidirectionally delay-coupled phase locked loop (PLL) systems with voltage controlled oscillator frequencies of 24 GHz to validate a non-hierarchical clock distribution approach. For this purpose, a PLL architecture that allows mutual coupling between two such nodes is introduced. An existing phase domain model is extended to include the nonlinear response of the oscillator to the tuning signal. With this extension the frequencies and phase-relations of self-organized synchronized states can be precisely predicted. This is verified by measurements obtained from two synchronized PLLs for different time delays and division factors. The predictions of the model are in good agreement with the measurements. For time delays up to 14 ns it is shown that self-organized synchronization is feasible at microwave frequencies.
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