A reconfigurable distributed architecture for clock generation in large many-core SoC

Abstract

Abstract-This paper focuses on clock generation and distribution in large SoC. After a brief analysis of diverse existed approaches, we propose a distributed architecture based on coupled local clock generators. Three prototypes are presented to demonstrate the feasibility of a large globally synchronous SoC with high reliability by using this approach. Moreover, the reconfigurability feature of this architecture provides a platform for exploring topologies with potentially improved performance.

Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs

“…Now the new variable x n describes the normalised time difference between the reference and local signals. When the delay D = 0, the first equation corresponds to (1). In our previous studies [4], [5], we introduced a model of the ADPLL implemented and verified in [1] (for the block diagram of the system, please refer again to Fig.…”

“…All Digital Phase Locked Loops (ADPLLs) are compulsory components in many microelectronic systems since they generate clocking signals. In recent applications, ADPLLs are interconnected into trees or networks to generate a synchronised distributed signal [1]- [9]. The research on ADPLLs and their networks is driven by the following major issues: how to ensure the synchronisation and stability of a single ADPLL or a network [10]- [15] and how to minimise their jitter [16]- [25].…”

“…In recent years ADPLLs have found implementation as a part of even more complex digital circuits -All-Digital PLL networks [1]- [3], [11]. This idea was inherited from works by Pratt and Nguyen [15], Gutnik and Chandrakasan [29] and Fridman [30].…”

“…In Section III, we show the feasibility of an ergodic approach in studying the average dynamics of the first-order Σ∆ modulator with respect to an arbitrary input signal. In Section IV, we apply the method established in Section III to study the stability of the ADPLL developed in [1]. Finally, the conclusions are made in Section V.…”

Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology

“…The network in that study was made of 16 distributed oscillators operating at 1.3 GHz fabricated in 0.35 µm CMOS technology. The new wave of distributed frequency generation has been based on all-digital PLLs with successful designs demonstrated in [6], [17].…”