A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays

Koskin, Eugene; Galayko, Dimitri; Blokhina, Elena

doi:10.1109/access.2018.2804324

Cited by 15 publications

(9 citation statements)

References 31 publications

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“…In recent years the body of theoretical studies on mutual synchronization has grown tremendously, offering new insights into the complex dynamics in networks with time-delayed, nonlinear interactions [16]- [18]. Particularly the analysis of networks of mutually coupled phase-locked loop (PLL) nodes has drawn increased attention [19]- [24]. Within a phase-model new insights into the self-organized dynamics of mutually delay-coupled PLLs in the presence of time delays, such as multistability of synchronized states, their frequencies, phase-relations and linear stability, can be obtained [25]- [31].…”

Section: Model Of Two Mutually Coupled Oscillatorsmentioning

confidence: 99%

Mutual Synchronization with 24 GHz Oscillators

Hoyer

Prousalis

Wetzel

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This work presents synchronization of two bidirectionally delay-coupled phase locked loop (PLL) systems with voltage controlled oscillator frequencies of 24 GHz to validate a non-hierarchical clock distribution approach. For this purpose, a PLL architecture that allows mutual coupling between two such nodes is introduced. An existing phase domain model is extended to include the nonlinear response of the oscillator to the tuning signal. With this extension the frequencies and phase-relations of self-organized synchronized states can be precisely predicted. This is verified by measurements obtained from two synchronized PLLs for different time delays and division factors. The predictions of the model are in good agreement with the measurements. For time delays up to 14 ns it is shown that self-organized synchronization is feasible at microwave frequencies.

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Section: Model Of Two Mutually Coupled Oscillatorsmentioning

confidence: 99%

Mutual Synchronization with 24 GHz Oscillators

Hoyer

Prousalis

Wetzel

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…So a high performance frequency synthesizer with low-power comsumption is a must for NB-IoT wireless transceivers. ADPLLs have gradually begun to replace conventional charge-pump phase locked loops (CPPLL) in CMOS process due to its small area, flexible re-configurability, amenability to technology porting [3]- [5]. Counter-based ADPLL provides a phase estimate with an accuracy of one oscillator period, and the dynamic range of TDC only needs to cover the residual phase error of within one cycle of output clock [6], [7].…”

Section: Introductionmentioning

confidence: 99%

A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications

Yan

et al. 2019

IEEE Access

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This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse prediction algorithms help to accelerate the locking process to less than 20 µs. A digital-to-time converter (DTC) is used with a phase prediction algorithm to minimize the detection range of the time-to-digital converter for low power consumption. The dither block is designed to improve the nonlinearity of DTC resulting in a −40-dBc in-band spur suppression. A low supply of 0.6-V digitally controlled oscillator has the frequency coverage of 1.5-2.05 GHz. Fabricated in a 55-nm CMOS, the ADPLL occupies an active area of 0.88 mm 2 and consumes 4 mW at 1.8 GHz. With a 24-MHz reference clock, the measurement results show that this work achieves better than −94-dBc/Hz in-band phase noise and −120.5 dBc/Hz at 1-MHz offset of 1.83-GHz carrier frequency. The FoM value is −233.4 dB, and the reference spur is −76.3 dBc. INDEX TERMS All digital phase-locked loop (ADPLL), digital-to-time converter (DTC), time-to-digital converter (TDC), digitally controlled oscillator (DCO), time amplifier (TA), narrow-band Internet-of-things (NB-IoT).

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“…Coupled oscillators are a repeating trend in micro-and nano-electronics, with more and more applications being discovered over recent years -neuromorphic computing [1], distributed computations [2], ultra-low phase noise frequency generation [3], clocking of peer-to-peer networks and radiocommunications [4], [5], distributed frequency generation [6]- [8] and others.…”

Section: Introductionmentioning

confidence: 99%

“…Study [20] introduced a novel nonlinear event-driven discrete-time AD-PLL model that is not based on any simplifications typical for ADPLL modelling. The proposed model was then used in [5], [21] to demonstrate the global stability and synchronization of ADPLL networks. Summarizing the recent research, we outline the following:…”

Section: Introductionmentioning

confidence: 99%

Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology

Galayko

Shan

Zianbetov

et al. 2019

IEEE Trans. Circuits Syst. II

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This paper presents an active distributed clock generator for manycore systems-on-chip consisting of a 10×10 network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequency range of 700-840 MHz at VDD = 1.1 V. The network is highly robust against VDD variations. An energy cost of 2.7 µW/MHz per node is 7 times lower than that in analog implementations of similar architectures and is twice lower than that in conventional H-tree architectures. This is the largest on-chip all-digital phase-locked loop network ever implemented. With clock generation nodes linked only locally, this solution is proven to be scalable. The presented clock generation network does not require any external reference, except for the startup frequency selection, generating a synchronized signal in fully autonomous mode and maintaining frequency stability within 0.09% during 1700 seconds. Such a network of frequency and phase synchronized oscillators can be used as a source for local clocking areas.

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A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays

Cited by 15 publications

References 31 publications

Mutual Synchronization with 24 GHz Oscillators

Mutual Synchronization with 24 GHz Oscillators

A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications

Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology

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