Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology

Abstract

This paper presents an active distributed clock generator for manycore systems-on-chip consisting of a 10×10 network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequency range of 700-840 MHz at VDD = 1.1 V. The network is highly robust against VDD variations. An energy cost of 2.7 µW/MHz per node is 7 times lower than that in analog implementations of similar architectures and is twice lower than that in conventional H-tree architectures. This is the largest on-chip all-digital phase-locked loop network ever implemented. With clock generation nodes linked only locally, this solution is proven to be scalable. The presented clock generation network does not require any external reference, except for the startup frequency selection, generating a synchronized signal in fully autonomous mode and maintaining frequency stability within 0.09% during 1700 seconds. Such a network of frequency and phase synchronized oscillators can be used as a source for local clocking areas.

Research on Clock Synchronization of Data Acquisition Based on NoC

“…IEEE 1588 [10,11] and White Rabbit (WR) [12] are the most commonly used distributed clock synchronization protocols. An active distributed clock generator was proposed in [13] for a multi-core SoC, which can achieve a less than 38 ps phase error between adjacent oscillators at 700-840 Mhz and VDD = 1.1 V. A Bayesian estimation time synchronization (BETS) algorithm was introduced in [14], which uses synchronization error compensation to reduce message interaction in clock synchronization and satisfies the resource constraints of wireless sensor networks. A distributed clock synchronization protocol based on an intelligent clustering algorithm was presented in [15], which allocates different synchronization frequencies according to the established cluster, in order to avoid excessive network access contention.…”

Wave propagation on networks of probabilistic inverter cells

“…In order to mitigate the problems of the clock distribution for CMOS LSI circuits, autonomously oscillating two-dimensional networks of logic gates [10][11][12] are extended throughout LSI chips. Mutually connected Phase-locked loops [13,14] can also be used as oscillating networks. The concept of the clock networks, especially networks of logic gates, will solve the above mentioned problems of the clocking for quantum effect circuits.…”