A synchronous approach for clocking VLSI systems

Anceau, François

doi:10.1109/jssc.1982.1051685

Cited by 50 publications

(14 citation statements)

References 4 publications

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“…For two reasons, it is appropriate to follow up on the implications of Eqs. (32). First, scattering theory provides a straightforward way to evaluate eigenvalues of a composite structure consisting of two non-overlapping potentials, and second, it provides further verification that scattering analysis of the coupled mode problem is consistent with known results.…”

mentioning

confidence: 61%

Spectral Inverse Scattering Theory for Dielectric Media: Application to Optical Devices

Tamil¹

1993

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mentioning

confidence: 61%

Spectral Inverse Scattering Theory for Dielectric Media: Application to Optical Devices

Tamil¹

1993

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“…This transposes traditional digital development frameworks (e.g. [14]) for the "systems-in-a-chip" environment.…”

Section: Multiple Clock Frequenciesmentioning

confidence: 96%

Clock Distribution Strategy for IP-based Development

Aguiar

Santos

2000

VLSI: Systems on a Chip

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Abstract:This paper presents a high-level clock distribution strategy for usage in a design-and-reuse environment. This strategy allows for controlled clock distribution across an arbitrary number of blocks through the usage of controlled delay lines. A new clock frequency multiplication structure optimised for this clock distribution strategy is finally proposed, since multifrequency clock support is highly desired.

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“…Use of both polysilicon wires and metal wires, as in CMOS ASICs, may create additional uncertainties in signal delays because polysilicon wires are slower than metal wires in propagating signals. To cope with this complexity, integrated circuit designers and researchers have developed volumes of knowledge, techniques and theories on a variety of clocking methodologies (Anceau 1982, Marques and Cunha 1983, Seitz 1980, Unger and Tan 1986, Weste and Eshraghian 1985. A particular methodology may be better suited for a given technology and system.…”

Section: Introductionmentioning

confidence: 99%

A single-phase two frequency clocking scheme for race-free glitch-free outputs of synchronous digital systems

Dam

Saha

1992

International Journal of Electronics

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A new clocking scheme is developed to produce race-free, glitch-free outputs of synchronous digital systems. The maximum input clock frequency for race-free operation is calculated as a single-phase system. Output signals are sampled at twice the input clock frequency, at time instants when the glitches are not there. Using the scheme, glitches generated anywhere within a quarter (T/4) of the input clock period (T) can be eliminated. The margin T/4 is large enough for most practical systems. Hence the scheme is of universal application as verified by the simulation of two 3 Jlm CMOS gate array ASICs, designed using VINYAS CAD tools.

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A synchronous approach for clocking VLSI systems

Cited by 50 publications

References 4 publications

Spectral Inverse Scattering Theory for Dielectric Media: Application to Optical Devices

Spectral Inverse Scattering Theory for Dielectric Media: Application to Optical Devices

Clock Distribution Strategy for IP-based Development

A single-phase two frequency clocking scheme for race-free glitch-free outputs of synchronous digital systems

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