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This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are 1) the writeand-verify (WAV) writing of four-level resistance states and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diodeswitch phase change memory cells with 90nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 10 8 cycles, respectively. In addition, they are nondestructively readable above 10 7 read pulses at 100ns and 1uA. IntroductionPhase-change random access memory (PRAM) is most promising to realize a multi-level cell (MLC) operation because it has very wide range of resistance across two orders of magnitude or the higher, with respect to writing current. According to the PRAM road map [1], it is expected that highest memory densities of PRAM become comparable to conventional memories such as NOR Flash and DRAM in coming years when MLC operation is fully accomplished. In this paper, we systematically investigated a four-level (two-bit) cell operation in diode-switch phase change memory cells with 90nm technology and discussed its possibilities and issues as well.

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An advanced bottom electrode contact (BEC) was successfully developed for reliable high-density 256 Mb phase-change random access memory (PRAM) using a ring-type contact scheme. This advanced ring-type BEC was prepared by depositing very thin TiN films inside a contact hole, after which core dielectrics were uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce reset current while maintaining a low set resistance and a uniform cell distribution. Thus, it has been clearly demonstrated that the use of the ring-type contact technology is very feasible for high-density PRAM beyond 256 Mb.

Phase-change random access memory is considered a potential challenger for conventional memories, such as dynamic random access memory and flash memory due to its numerous advantages. Nevertheless, high reset current is the ultimate problem in developing high-density phase-change random access memory (PRAM). We focus on the adoption of Ge2Sb2Te5 confined structures to achieve lower reset currents. By changing from a normal to a GST confined structure, the reset current drops to as low as 0.8 mA. Eventually, our integrated 64 Mb PRAM based on 0.18 µm CMOS technology offers a large sensing margin: R reset ∼200 kΩ and R set ∼2 kΩ, as well as reasonable reliability: an endurance of 1.0×109 cycles and a retention time of 2 years at 85°C.