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The ring amplifier is an energy efficient and high output swing alternative to an OTA for switched-capacitor circuits. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. This paper presents a self-biased ring amplifier scheme that makes the ring amplifier more practical and power efficient while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. We introduce an improved auto-zero scheme that eliminates the gain error caused by the parasitic capacitance across the auto-zero switch. Furthermore, a comparator-less pipeline ADC structure takes advantage of the characteristics of the ring-amplifier to replace the sub-ADC in each pipeline stage. The prototype ADC has measured SNDR, SNR and SFDR of 56.6 dB (9.11 b), 57.5 dB and 64.7 dB, respectively, for a Nyquist frequency input sampled at 100 MS/s, and consumes 2.46 mW.Index Terms-A/D, ADC, analog to digital converter, auto-zero, comparator-less ADC, energy efficient, low power, ring amplifier, self-biased ring amplifier, switched capacitor.

The noise performance of CMOS image sensors has improved significantly. The most popular way to reduce readout circuit noise is amplifying pixel output using a preamplifier at the foremost stage of readout chain to suppress the noise of following readout chains in high analog gain [1][2][3]. Another approach is multiple sampling which can reduce temporal noise of pixel and readout circuit by sampling the same pixel repeatedly and processing (generally averaging) the sampled data [4,5]. However, both approaches require additional circuitry in the column readout chain which requires extra silicon area and power consumption. Furthermore, it is hard to implement a decent per-column amplifier in a small pixel pitch sensor, such as 1.4µm pixel, because of narrow layout space. In addition, the second approach requires longer readout time proportional to the number of samples. This paper presents a cost-effective low noise CMOS image sensor readout chain using pseudo-multiple sampling technique.The proposed pseudo-multiple sampling technique is described in Fig. 22.2.1. The basic concept of pseudo-multiple sampling is dividing an A/D conversion into several lower resolution A/D conversions. The quantization step of each lower resolution A/D conversion is M times larger than that of normal A/D conversion where M is the number of pseudo-multiple sampling. Each quantization level of lower resolution A/D conversion has 1 LSB offset of normal A/D conversion to ensure the final result has the same resolution of normal A/D conversion. The final result can be calculated by adding all lower resolution A/D conversion results.The output noise of each lower resolution A/D conversion is approximately 1/M times lower than that of normal A/D conversion, when the input noise standard deviation is higher than the quantization step of lower resolution A/D conversion. Therefore, the output noise of the pseudo-multiple sampling A/D conversion is 1/√M times lower than that of normal A/D conversion, if the noise is completely uncorrelated. It is same as the conventional multiple sampling. However, the noise reduction effect of the pseudo-multiple sampling is limited, although the number of sampling is increased. It is because if the quantization step of lower resolution A/D conversion is higher than the input noise standard deviation, some of lower resolution A/D conversion cannot express the input noise properly. Figure 22.2.2 is the noise reduction simulation result of the conventional multiple sampling and the pseudo-multiple sampling using an ideal A/D converter with input noise applied. The noise is assumed white Gaussian having standard deviation of σ in in normal A/D conversion LSB unit. The simulation result shows the noise reduction performance of the pseudo-multiple sampling is almost same as that of the conventional multiple sampling up to M=σ in , and the output noise is saturated to 0.75×√σ in when M is higher than 4σ in .The pseudo-multiple sampling can be implemented using a conventional single slope ADC structure by altering o...

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Analog compute-in-memory with resistive random access memory (RRAM) devices promises to overcome the data movement bottleneck in data-intensive artificial intelligence (AI) and machine learning. RRAM crossbar arrays improve the efficiency of vector-matrix multiplications (VMMs), which is a vital operation in these applications. The prototype IC is the first complete, fully integrated analog-RRAM CMOS coprocessor. This article focuses on the digital and analog circuitry that supports efficient and flexible RRAM-based computation. A passive 54 × 108 RRAM crossbar array performs VMM in the analog domain. Specialized mixed-signal circuits stimulate and read the outputs of the RRAM crossbar. The single-chip CMOS prototype includes a reduced instruction set computer (RISC) processor interfaced to a memory-mapped mixed-signal core. In the mixed-signal core, ADCs and DACs interface with the passive RRAM crossbar. The RISC processor controls the mixed-signal circuits and the algorithm data path. The system is fully programmable and supports forward and backward propagation. As proof of concept, a fully integrated 0.18-µm CMOS prototype with a postprocessed RRAM array demonstrates several key functions of machine learning, including online learning. The mixed-signal core consumes 64 mW at an operating frequency of 148 MHz. The total system power consumption considering the mixed-signal circuitry, the digital processor, and the passive RRAM array is 307 mW. The maximum theoretical throughput is 2.6 GOPS at an efficiency of 8.5 GOPS/W.

Summary A patient presented to the ear, nose and throat department with inspiratory stridor, dysphagia and a sore throat. Clinical and radiological examination was normal. During induction of anaesthesia for a planned microlaryngoscopy, the patient developed complete upper airway obstruction that was overcome by applying positive pressure via a facepiece until awake. He subsequently developed respiratory failure, requiring mechanical ventilatory support. An elective tracheostomy was inserted for his symptoms. Neurological opinion confirmed the diagnosis of multiple system atrophy with akinetic rigid syndrome. We review this obscure condition and how it may occasionally present to anaesthetists.