A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC

Lim, Yong; Flynn, Michael P.

doi:10.1109/jssc.2015.2463094

Cited by 141 publications

(36 citation statements)

References 12 publications

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“…The structure of sample-and hold circuit can be divided into two categories: charge redistribution structure and capacitance reversal structure [1,[10][11][12] . Figure 1 is a charge redistribution structure.…”

Section: The Structure Of the Sample-and Hold Circuitmentioning

confidence: 99%

A Sample-and- Hold Circuit for a Resolution Pipelined ADC

Zhai¹,

Ding³

et al. 2018

Proceedings of the 2018 7th International Conference on Energy, Environment and Sustainable Development (ICEESD 2018)

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Section: The Structure Of the Sample-and Hold Circuitmentioning

confidence: 99%

A Sample-and- Hold Circuit for a Resolution Pipelined ADC

Zhai¹,

Ding³

et al. 2018

Proceedings of the 2018 7th International Conference on Energy, Environment and Sustainable Development (ICEESD 2018)

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“…Otherwise, digital calibration such as a background calibration is necessary to achieve accurate residue gain. Another alternative is the ring amplifier [33,34] which essentially is a 3-stage inverter amplifier. Such amplifier results in a good energy efficiency and the required high open-loop DC gain can be easily achieved from three gain stages.…”

Section: Challenges and Previous Workmentioning

confidence: 99%

Energy-Efficient Data Converters for Low-Power Sensors

Chen

2017

Linköping Studies in Science and Technology. Dissertations

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Wireless sensor networks (WSNs) are employed in many applications, such as for monitoring bio-potential signals and environmental information. These applications require high-resolution (> 12-bit) analog-to-digital converters (ADCs) at low-sampling rates (several kS/s). Such sensor nodes are usually powered by batteries or energyharvesting sources hence low power consumption is primary for such ADCs. Normally, tens or hundreds of autonomously powered sensor nodes are utilized to capture and transmit data to the central processor. Hence it is profitable to fabricate the relevant electronics, such as the ADCs, in a low-cost standard complementary metal-oxidesemiconductor (CMOS) process. The two-stage pipelined successive approximation register (SAR) ADC has shown to be an energy-efficient architecture for high resolution. This thesis further studies and explores the design limitations of the pipelined SAR ADC for high-resolution and low-speed applications. The first work is a 15-bit, 1 kS/s two-stage pipelined SAR ADC that has been implemented in 0.35-µm CMOS process. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array digital-to-analog converter (DAC) topology in the second-stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. A comprehensive power consumption analysis of the entire ADC is performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitorbased DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-µm CMOS process, the prototype ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8-bit at a sampling frequency of 1 kS/s and provides a Schreier figure-of-merit (FoM) of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1-bit up to the Nyquist bandwidth of 500 Hz while consuming 6.7 µW. Core area of the ADC is 0.679 mm 2. The second work is a 14-bit, tunable bandwidth two-stage pipelined SAR ADC which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high open-loop DC gain requirement of the OTA in the gain-stage, a 3-stage x

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“…The traditional pipelined structure has a speed merit, but the multiple amplifiers consume much power. Recently, pipelined-SAR structure has obtained much attention because it combines both the merits of pipelines and SAR ADCs [5][6][7][8][9][10][11][12][13][14][15][16][17]. As in traditional pipelined ADCs, two SAR ADCs connected by a residue amplifier (RA) can work concurrently.…”

Section: Introductionmentioning

confidence: 99%

A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

2020

Electronics

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A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm2. The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect to process-voltage-temperature (PVT). A background calibration of the inter-stage gain is proposed to adjust the inter-stage gain and to track the PVT variables. The measurement results show that, with calibration, the spurious-free-dynamic-range (SFDR) and signal-to-noise-and-distortion-ratio (SINAD) can be improved from 68 dB and 61 dB to 78 dB and 63 dB, respectively. The dynamic performance was stable under different VT conditions.

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A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC

Cited by 141 publications

References 12 publications

A Sample-and- Hold Circuit for a Resolution Pipelined ADC

A Sample-and- Hold Circuit for a Resolution Pipelined ADC

Energy-Efficient Data Converters for Low-Power Sensors

A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

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