A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

Wu, Junjie; Wu, Jianhui

doi:10.3390/electronics9030507

Cited by 4 publications

(2 citation statements)

References 22 publications

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“…The chip makes use of several capacitor units to form capacitors and achieves accurate proportional matching of coefficients. The differential structure of the capacitor array is completely symmetrically distributed on both sides of the comparator, which is used to improve the overall anti-noise capability of the circuit [ 33 ]. The digital control logic is uniformly placed at the back end of the chip, and the digital part and the analogue part are effectively isolated to reduce the interference of digital noise on the front-end analogue module.…”

Section: Layout Designmentioning

confidence: 99%

A Low Power Sigma-Delta Modulator with Hybrid Architecture

Xia

et al. 2020

Sensors

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Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

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Section: Layout Designmentioning

confidence: 99%

A Low Power Sigma-Delta Modulator with Hybrid Architecture

Xia

et al. 2020

Sensors

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“…Among the several architectural approaches, the SAR-assisted pipeline configurations have been proven a promising high-speed high-resolution ADC structure with excellent energy efficiency [6][7][8][9][10][11][12][13][14][15][16][17]. As shown Figure 1, this type of hybrid ADC uses the low-resolution energy-efficient SAR ADCs and the residue amplifiers (RAs).…”

Section: Introductionmentioning

confidence: 99%

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Seo

2021

Electronics

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This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

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A SAR ADC with a higher precision bootstrap switch and highest split capacitor array

Guo

et al. 2023

Third International Conference on Digital Signal and Computer Communications (DSCC 2023)

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The design of this paper is a 12bit SAR ADC,in order to optimize its performance and be able to achieve high accuracy, there are certain requirements for certain modules of the ADC. The design uses the bottom plate sampling, access to the common mode level Vcm on the upper pole plate of the DAC capacitor array is accessed by a higher precision bootstrap switch to reduce the non-linearity brought by the Vcm level access switch. By performing FFT simulation on the sampling points, it can be used at a sampling rate of 50Ms/s when the input signal frequency is 0.8301MHz and ENOB is 15.64bit. The capacitor array uses a combination of segmentation and splitting to greatly reduce the number of total capacitors, achieving only 188 unit capacitors, a 97.7% reduction in number compared to the conventional structure, for the entire ADC digital circuit The power consumption as well as the area of the ADC digital circuit has been significantly improved. The comparator uses a dynamic latching comparator to reduce power consumption while reducing the equivalent input noise of the comparator. The logic circuit uses dynamic SAR logic to control the analog-to-digital converter's successive comparisons. Sampling and analysis of the entire SAR ADC output achieves a valid bit count of 11.93 bits at a low frequency input signal of 0.1953MHz, enabling the conversion of a 12bit SAR ADC.

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A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

Cited by 4 publications

References 22 publications

A Low Power Sigma-Delta Modulator with Hybrid Architecture

A Low Power Sigma-Delta Modulator with Hybrid Architecture

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

A SAR ADC with a higher precision bootstrap switch and highest split capacitor array

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