A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Abstract

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

A Reconfigurable Hybrid ADC Using a Jump Search Algorithm

“…Among recently researched ADCs [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20], various hybrid structures [11][12][13][14][15][16][17][18][19] are being explored. However, the SAR ADC architecture is required due to the low power consumption, bandwidth, and resolution for biomedical signal processing.…”

A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

“…In order to realize a low-power TI ADC of several tens of GS/s, a single channel ADC used as a sub-ADC must be designed to be very compact and high-speed. During the past decade, successive approximation register (SAR) analog-to-digital converters (ADCs) have become a dominant ADC architecture as sub-ADCs of the TI ADC, covering a wide range of resolution and speed owing to advanced process technologies, mostly attributed to their digital friendly architecture [4][5][6][7][8][9][10][11]. The need for high-speed clocks for internal loop operation in a synchronous SAR ADC can be eliminated by using asynchronous architecture [12][13][14].…”