A sample-and-hold circuit for a resolution pipelined ADC is presented. The circuit uses a fully differential capacitor flip structure to reduce power consumption. Increase the gain by using an olded-cascode amplifier. Based on 0.35μm CMOS process, the Hspice simulation shows that the circuit can work correctly at 3.3v power.
A circuit of fast-setting charge pump on-chip is designed based on the Dickson circuit. The charge pump circuit, which is improved, increases the initial node voltage. With the consideration of the current mismatch, the accurate clock of the duty circle below 50% is proposed. The HSPICE simulation result indicates that the setting time from 0V to 20V only needs 51.650μs for the charge pump, and it is faster than the traditional Dickson charge pump 26.03μs. In summary, the settling time of the output voltage of the charge pump is prominently decreased and the performance of the charge pump is obviously improved.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.