A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers

Lim, Yong; Flynn, Michael P.

doi:10.1109/jssc.2015.2453332

Cited by 106 publications

(44 citation statements)

References 14 publications

(36 reference statements)

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“…Capacitors (C C ) are added to the input nodes of amplifier for saving the operation point of ring-amplifier. In the previous works [9] and [10], the common feedback circuit (CMFB) of pseudo differential ring-amplifier is consist of the capacitors C cm1 s and C cm2 s as shown in Fig. 7(a).…”

Section: Pseudo Differential Ring Amplifiermentioning

confidence: 99%

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer

Pan

San

2019

IEICE Trans. Fundamentals

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This paper presents a 6th-order quadrature bandpass delta sigma AD modulator (QBPDSM) with 2nd-order image rejection using dynamic amplifier and noise coupling (NC) SAR quantizer embedded by passive adder for the application of wireless communication system. A novel complex integrator using dynamic amplifier is proposed to improve the energy efficiency of the QBPDSM. The NC SAR quantizer can realize an additional 2nd-order noise shaping and 2nd-order image rejection by the digital domain noise coupling technique. As a result, the 6th-order QBPDSM with 2nd-order image rejection is realized by two complex integrators using dynamic amplifier and the NC SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed QBPDSM in 90 nm CMOS technology. Simulated SNDR of 76.30 dB is realized while a sinusoid −3.25 dBFS input is sampled at 33.3 MS/s and the bandwidth of 2.083 MHz (OSR=8) is achieved. The total power consumption in the modulator is 6.74 mW while the supply voltage is 1.2 V. key words: quadrature bandpass delta sigma modulator, image rejection, SAR quantizer, noise coupling, ring amplifier, complex integrator

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Section: Pseudo Differential Ring Amplifiermentioning

confidence: 99%

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer

Pan

San

2019

IEICE Trans. Fundamentals

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“…In this work, we use the pseudo differential ring amplifier proposed in the previous work [8], [10] to realize the integrator for achieving the maximum power-efficiency of the amplifier in the ΔΣAD modulator. Figure 6 (a) shows the pseudo differential ring amplifier.…”

Section: Pseudo Differential Ring Amplifiermentioning

confidence: 99%

“…Capacitors (C C ) are added to the input nodes of amplifier to realize the amplifier input offset cancellation for the integrator. In the previous works [8] and [10], the voltage division from the C C and the capacitors of the common mode feedback (CMFB) circuit cause the reduction of common mode rejection ratio (CMRR). This paper proposes the modifying CMFB circuit as shown in Fig.…”

Section: Pseudo Differential Ring Amplifiermentioning

confidence: 99%

A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer

Pan

San

2018

IEICE Trans. Electron.

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The usage of this PDF file must comply with the IEICE Provisions on Copyright. The author(s) can distribute this PDF file for research and educational (nonprofit) purposes only. Distribution by anyone other than the author(s) is prohibited. 480 SUMMARYThis paper presents a 3rd-order ΔΣAD modulator with noise coupling structure using the proposed passive adder embedded quantization noise shaping (QNS) SAR quantizer. QNS SAR quantizer can feedback shaped quantization noise and realize an additional 1st-order noise shaping by noise coupling technique. As a result, the 3rd-order noise coupled ΔΣAD modulator is realized by two integrators with ring amplifier and the QNS SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed ΔΣAD modulator in 90nm CMOS technology. Simulated SNDR of 81.05dB is achieved while a sinusoid −4.32dBFS input is sampled at 100MS/s and the bandwidth is BW = 3.125MHz. The total power consumption in the modulator is 4.58mW while the supply voltage is 1.2V.

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“…But the stability becomes an issue. To solve this problem, a self-biased ring amplifier is reported in [35].…”

Section: Challenges and Previous Workmentioning

confidence: 99%

Energy-Efficient Data Converters for Low-Power Sensors

Chen

2017

Linköping Studies in Science and Technology. Dissertations

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Wireless sensor networks (WSNs) are employed in many applications, such as for monitoring bio-potential signals and environmental information. These applications require high-resolution (> 12-bit) analog-to-digital converters (ADCs) at low-sampling rates (several kS/s). Such sensor nodes are usually powered by batteries or energyharvesting sources hence low power consumption is primary for such ADCs. Normally, tens or hundreds of autonomously powered sensor nodes are utilized to capture and transmit data to the central processor. Hence it is profitable to fabricate the relevant electronics, such as the ADCs, in a low-cost standard complementary metal-oxidesemiconductor (CMOS) process. The two-stage pipelined successive approximation register (SAR) ADC has shown to be an energy-efficient architecture for high resolution. This thesis further studies and explores the design limitations of the pipelined SAR ADC for high-resolution and low-speed applications. The first work is a 15-bit, 1 kS/s two-stage pipelined SAR ADC that has been implemented in 0.35-µm CMOS process. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array digital-to-analog converter (DAC) topology in the second-stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. A comprehensive power consumption analysis of the entire ADC is performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitorbased DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-µm CMOS process, the prototype ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8-bit at a sampling frequency of 1 kS/s and provides a Schreier figure-of-merit (FoM) of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1-bit up to the Nyquist bandwidth of 500 Hz while consuming 6.7 µW. Core area of the ADC is 0.679 mm 2. The second work is a 14-bit, tunable bandwidth two-stage pipelined SAR ADC which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high open-loop DC gain requirement of the OTA in the gain-stage, a 3-stage x

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A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers

Cited by 106 publications

References 14 publications

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer

A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer

Energy-Efficient Data Converters for Low-Power Sensors

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