Two-bit cell operation in diode-switch phase change memory cells with 90nm technology

Abstract

This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are 1) the writeand-verify (WAV) writing of four-level resistance states and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diodeswitch phase change memory cells with 90nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 10 8 cycles, respectively. In addition, they are nondestructively readable above 10 7 read pulses at 100ns and 1uA. IntroductionPhase-change random access memory (PRAM) is most promising to realize a multi-level cell (MLC) operation because it has very wide range of resistance across two orders of magnitude or the higher, with respect to writing current. According to the PRAM road map [1], it is expected that highest memory densities of PRAM become comparable to conventional memories such as NOR Flash and DRAM in coming years when MLC operation is fully accomplished. In this paper, we systematically investigated a four-level (two-bit) cell operation in diode-switch phase change memory cells with 90nm technology and discussed its possibilities and issues as well.

Role of activation energy in resistance drift of amorphous phase change materials

“…In principle, a variation of the amorphous volume enables the storage of multiple resistance states in a single cell. This way the storage density of the memory could be greatly increased [6][7][8][9][10][11]. In practice, the phenomenon of resistance drift, i.e., the change of resistivity of amorphous phase change materials over time, precludes a simple implementation of the multibit storage on a chip level.…”

High-field electrical transport in amorphous phase-change materials

“…Phase change memory technology (PCRAM) is an active field of research with the objective to realize CMOS compatible, multi-bit nonvolatile memories. [1][2][3][4][5] In a PCRAM cell, a nano-sized volume of phase change material (chalcogenides such as Ge 2 Sb 2 Te 5 or GeTe) is switched quickly (order of ns (Ref. 6)) and reversibly (1 Â 10 11 times (Ref.…”

Superposition coding in rewritable channels

“…Further define π(φ) = {a : F A (a) ∈ γ(φ)} Then for any µ A -measurable set δ where the last equality follows from (8) and (11). At this moment, we invoke Lemma 3 to deduce that This proves the lemma.…”

“…In the latter, multiple bits/cell storage is attained in practical devices by employing an iterative feedback algorithm that is referred to as a "write-and-verify" strategy. Also in demonstrations of multiple bit/cell PCM [9][10] [11], similar techniques are exploited.…”