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This paper addresses and evaluates the temperature dependence performance of silicon carbide (4H-SiC) based insulated gate bipolar transistors (IGBTs) using two dimensional numerical computer aided design tool (i.e., Atlas TCAD from Silvaco). Using identical set of device physical parameters (doping, thicknesses), simulated structure was first caliberated with the experimental data. A minority carrier life time in the drift layer of 1.0 – 1.6 µs and contact resistivity of 0.5 - 1.0 x 10-4 Ω-cm2 produces a close match with the experimental device. A set of n type IGBT structures were then numerically simulated to extract the conduction losses for various blocking voltage classes. An on-resistance first decays with temperature (i.e., increased in ionization level, and increase in minority carrier life time), stays nearly constant with further increase in the temperature (may be all carriers are now fully ionized and increase in carrier life time is compensated with decrease in the carrier mobility) and finally increases linearly with temperature (>450 oC) due to decrease in the carrier mobility. Compared with Si based IGBTs, numerical simulation predicts lower VCEON and RON values for 4H-SiC based IGBTs for higher voltage classes and hence potential for achieving smaller conduction losses for SiC based IGBTs.

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The paper deals with an experimental analysis on the behavior of parallel connections of super-junction power MOSFET devices in a boost converter used as power factor corrector (PFC). The main impact of the parameter variation on the parallel connection has been treated. The experimental evaluation of the current sharing in parallel connection has been carried out in several operative conditions by considering the influence of different parameters. Finally, a specific arrangement able to reduce the current imbalance of the devices has been experimented and discussed.

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