Superconducting quantum computing architectures comprise resonators and qubits that experience energy loss due to two-level systems (TLS) in bulk and interfacial dielectrics. Understanding these losses is critical to improving performance in superconducting circuits. In this work, we present a method for quantifying the TLS losses of different bulk and interfacial dielectrics present in superconducting coplanar waveguide (CPW) resonators. By combining statistical characterization of sets of specifically designed CPW resonators on isotropically etched silicon substrates with detailed electromagnetic modeling, we determine the separate loss contributions from individual material interfaces and bulk dielectrics. This technique for analyzing interfacial TLS losses can be used to guide targeted improvements to qubits, resonators, and their superconducting fabrication processes.

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Lossy dielectrics are a significant source of decoherence in superconducting quantum circuits. In this report, we model and compare the dielectric loss in bulk and interfacial dielectrics in titanium nitride (TiN) and aluminum (Al) superconducting coplanar waveguide resonators. We fabricate isotropically trenched resonators to produce a series of device geometries that accentuate a specific dielectric region's contribution to the resonator quality factor. While each dielectric region contributes significantly to loss in TiN devices, the metal–air interface dominates the loss in the Al devices. Furthermore, we evaluate the quality factor of each TiN resonator geometry with and without a post-process hydrofluoric etch and find that it reduced losses from the substrate–air interface, thereby improving the quality factor.

As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays-provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or lowloss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs-10 μm wide by 20 μm long by 200 μm deep-with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.

Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers and composite vias between distant superconducting layers. Effects of magnetic flux trapping in ground plane moats on coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations. Test circuits used for the measurements were fabricated in a new 150-nm node of a fully planarized process with eight niobium layers, SC2 process, developed at MIT Lincoln Laboratory for superconductor electronics and in its 250nm node SC1, as well as in the standard fabrication process SFQ5ee. The SC2 process utilizes 193-nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. All other processes use 248-nm photolithography. Effects of variation of process parameters on circuit inductors are discussed. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Part II is devoted to mutual inductance of various closely spaced features in integrated circuits, meanders, and transformers.

We describe the implementation of new commercial pulse-bias electronics that have enabled an improvement in the generation of quantum-accurate waveforms both with and without low-frequency compensation biases. We have used these electronics to apply a multilevel pulse bias to the Josephson arbitrary waveform synthesizer and have generated, for the first time, a quantum-accurate bipolar sinusoidal waveform without the use of a low-frequency compensation bias current. This uncompensated 1 kHz waveform was synthesized with an rms amplitude of 325 mV and maintained its quantum accuracy over a1.5 mA operating current range. The same technique and equipment was also used to synthesize a quantum-accurate 1 MHz sinusoid with a 1.2 mA operating margin. In addition, we have synthesized a compensated 1 kHz sinusoid with an rms amplitude of 1 V and a 2.7 mA operating margin.

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In order to increase circuit density of superconductor digital and neuromorphic circuits by 10× and reach integration scale of 10 8 Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors for cell miniaturization. The process has one layer of JJs, one layer of resistors, and ten fully planarized superconducting layers: 8 niobium layers and two layers of high kinetic inductance materials, Mo2N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. The minimum linewidth of NbN kinetic inductors is 250 nm. NbN films were deposited by two methods: with 𝑻𝑻 𝒄𝒄 ≈15.5 K by reactive sputtering of a Nb target in Ar+N2 mixture; with 𝑻𝑻 𝒄𝒄 in the range from 9 K to 13 K by plasmaenhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, h/w>1, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below 200 o C required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically ≤50 Ω, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to minimize parasitic kinetic inductance associated with interlayer vias and connections to JJs as well as to increase critical currents of the vias. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given.