2019
DOI: 10.1109/tasc.2019.2904919
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Advanced Fabrication Processes for Superconductor Electronics: Current Status and New Developments

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Cited by 82 publications
(61 citation statements)
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“…Furthermore, several research groups have reported successful demonstrations of large-scale, energy-efficient superconductor digital circuits [8][9][10], which indicates the high robustness, as well as the high energy efficiency, of superconductor logic families. Note that these demonstrations were supported by recent advances in fabrication technology for superconductor integrated circuits [11][12][13].…”
Section: Introductionmentioning
confidence: 82%
“…Furthermore, several research groups have reported successful demonstrations of large-scale, energy-efficient superconductor digital circuits [8][9][10], which indicates the high robustness, as well as the high energy efficiency, of superconductor logic families. Note that these demonstrations were supported by recent advances in fabrication technology for superconductor integrated circuits [11][12][13].…”
Section: Introductionmentioning
confidence: 82%
“…We briefly discuss the potential for a JJ/MJJ neural network as compared to modern CMOS. JJ/MJJ based neural networks can leverage the development of digital JJ circuits, which are near 106 JJ's per square cm 26,27 . While these densities are no-where near modern CMOS the JJ fabrication process continues to scale and at roughly 106 JJ's per cm2 some smaller scale applications may be within reach.…”
Section: Discussionmentioning
confidence: 99%
“…The fabrication process of the first module is very similar to our new process SC1 [24], whereas the second JJ module is identical to the SFQee process developed in [1], [2]. Vias to Nb layers M4, M5, etc., are named, respectively, I4, I5, etc.…”
Section: A Layer Stack and Jc Optionsmentioning
confidence: 99%
“…Our fabrication process for Nb/Al/AlOx/Nb junctions was described in detail in [1]- [3], [24]. We adjusted the Nb deposition process in order to obtain a more uniform stress distribution, primarily between the center and edge of the wafers.…”
Section: B Sis and Sfs Trilayers Fabricationmentioning
confidence: 99%