Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS &lt;italic&gt;π&lt;/italic&gt;-Junctions

Tolpygo, Sergey K.; Bolkhovsky, Vladimir; Rastogi, Ravi; Zarr, Scott; Day, Alexandra; Golden, Evan; Weir, Terence J.; Wynn, Alex; Johnson, L. M.

doi:10.1109/tasc.2019.2901709

Cited by 22 publications

(7 citation statements)

References 31 publications

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“…The other means of increasing the integration scale and circuit density further would be by increasing the number of Josephson junction layers to two and beyond. Some progress in this direction has already been demonstrated [47], [48].…”

Section: Discussionmentioning

confidence: 97%

Progress Toward Superconductor Electronics Fabrication Process With Planarized NbN and NbN/Nb Layers

Tolpygo

Mallek

Bolkhovsky

et al. 2023

IEEE Trans. Appl. Supercond.

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In order to increase circuit density of superconductor digital and neuromorphic circuits by 10× and reach integration scale of 10 8 Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors for cell miniaturization. The process has one layer of JJs, one layer of resistors, and ten fully planarized superconducting layers: 8 niobium layers and two layers of high kinetic inductance materials, Mo2N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. The minimum linewidth of NbN kinetic inductors is 250 nm. NbN films were deposited by two methods: with 𝑻𝑻 𝒄𝒄 ≈15.5 K by reactive sputtering of a Nb target in Ar+N2 mixture; with 𝑻𝑻 𝒄𝒄 in the range from 9 K to 13 K by plasmaenhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, h/w>1, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below 200 o C required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically ≤50 Ω, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to minimize parasitic kinetic inductance associated with interlayer vias and connections to JJs as well as to increase critical currents of the vias. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given.

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Section: Discussionmentioning

confidence: 97%

Progress Toward Superconductor Electronics Fabrication Process With Planarized NbN and NbN/Nb Layers

Tolpygo

Mallek

Bolkhovsky

et al. 2023

IEEE Trans. Appl. Supercond.

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“…Therefore, choosing the correct materials and fabrication method for reducing J C spread, controlling I C value, and superconductor film quality are the main challenges in fabrication. Recently, many attempts at large-scale fabrication have shown progress in this regard [32,33].…”

Section: All-jj Circuits 21 2f-junctionmentioning

confidence: 99%

High-density superconductive logic circuits utilizing 0 and π josephson junctions

Razmkhah,

Pedram

2024

Eng. Res. Express

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Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics' scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100 times in the SCE chips.

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“…Superconducting electronics, including active JJs, are routinely deposited at low temperatures (< 180 ℃). Integrated circuits with two stacked planes of JJs have been demonstrated by two research laboratories (Ando et al, 2017 ; Tolpygo et al, 2019 ), along with multiple of planes of SNSPDs (Verma et al, 2012 ). This is particularly important, as superconducting systems will not be able to reach 10 6 neurons per wafer without 3D integration.…”

Section: System Level Considerationsmentioning

confidence: 99%

Considerations for Neuromorphic Supercomputing in Semiconducting and Superconducting Optoelectronic Hardware

Primavera

Shainline

2021

Front. Neurosci.

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Any large-scale spiking neuromorphic system striving for complexity at the level of the human brain and beyond will need to be co-optimized for communication and computation. Such reasoning leads to the proposal for optoelectronic neuromorphic platforms that leverage the complementary properties of optics and electronics. Starting from the conjecture that future large-scale neuromorphic systems will utilize integrated photonics and fiber optics for communication in conjunction with analog electronics for computation, we consider two possible paths toward achieving this vision. The first is a semiconductor platform based on analog CMOS circuits and waveguide-integrated photodiodes. The second is a superconducting approach that utilizes Josephson junctions and waveguide-integrated superconducting single-photon detectors. We discuss available devices, assess scaling potential, and provide a list of key metrics and demonstrations for each platform. Both platforms hold potential, but their development will diverge in important respects. Semiconductor systems benefit from a robust fabrication ecosystem and can build on extensive progress made in purely electronic neuromorphic computing but will require III-V light source integration with electronics at an unprecedented scale, further advances in ultra-low capacitance photodiodes, and success from emerging memory technologies. Superconducting systems place near theoretically minimum burdens on light sources (a tremendous boon to one of the most speculative aspects of either platform) and provide new opportunities for integrated, high-endurance synaptic memory. However, superconducting optoelectronic systems will also contend with interfacing low-voltage electronic circuits to semiconductor light sources, the serial biasing of superconducting devices on an unprecedented scale, a less mature fabrication ecosystem, and cryogenic infrastructure.

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Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS <italic>π</italic>-Junctions

Cited by 22 publications

References 31 publications

Progress Toward Superconductor Electronics Fabrication Process With Planarized NbN and NbN/Nb Layers

Progress Toward Superconductor Electronics Fabrication Process With Planarized NbN and NbN/Nb Layers

High-density superconductive logic circuits utilizing 0 and π josephson junctions

Considerations for Neuromorphic Supercomputing in Semiconducting and Superconducting Optoelectronic Hardware

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