Superconducting quantum computing architectures comprise resonators and qubits that experience energy loss due to two-level systems (TLS) in bulk and interfacial dielectrics. Understanding these losses is critical to improving performance in superconducting circuits. In this work, we present a method for quantifying the TLS losses of different bulk and interfacial dielectrics present in superconducting coplanar waveguide (CPW) resonators. By combining statistical characterization of sets of specifically designed CPW resonators on isotropically etched silicon substrates with detailed electromagnetic modeling, we determine the separate loss contributions from individual material interfaces and bulk dielectrics. This technique for analyzing interfacial TLS losses can be used to guide targeted improvements to qubits, resonators, and their superconducting fabrication processes.
Lossy dielectrics are a significant source of decoherence in superconducting quantum circuits. In this report, we model and compare the dielectric loss in bulk and interfacial dielectrics in titanium nitride (TiN) and aluminum (Al) superconducting coplanar waveguide resonators. We fabricate isotropically trenched resonators to produce a series of device geometries that accentuate a specific dielectric region's contribution to the resonator quality factor. While each dielectric region contributes significantly to loss in TiN devices, the metal–air interface dominates the loss in the Al devices. Furthermore, we evaluate the quality factor of each TiN resonator geometry with and without a post-process hydrofluoric etch and find that it reduced losses from the substrate–air interface, thereby improving the quality factor.
As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays-provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or lowloss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs-10 μm wide by 20 μm long by 200 μm deep-with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
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