Inductance of superconductor integrated circuit features with sizes down to 120 nm

Abstract

Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers and composite vias between distant superconducting layers. Effects of magnetic flux trapping in ground plane moats on coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations. Test circuits used for the measurements were fabricated in a new 150-nm node of a fully planarized process with eight niobium layers, SC2 process, developed at MIT Lincoln Laboratory for superconductor electronics and in its 250nm node SC1, as well as in the standard fabrication process SFQ5ee. The SC2 process utilizes 193-nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. All other processes use 248-nm photolithography. Effects of variation of process parameters on circuit inductors are discussed. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Part II is devoted to mutual inductance of various closely spaced features in integrated circuits, meanders, and transformers.

Pulsar: A Superconducting Delay-Line Memory

“…This leads to data densities of up to 0.9 Mbit/cm 2 at 100 GHz, if all four metal routing layers are used, and matches the state of the art 12 . Reducing the Nb stripline linewidth and minimum spacing from 250 nm to 120 nm is a possible but more aggressive design choice 34 and results in densities of up to 1.9 Mbit/cm 2 , exceeding the state of the art by almost 2×.…”

“…By switching device material and topology to a MoN kinetic inductor microstrip with the same dimensions, available on just one layer within MIT Lincoln Laboratory's SFQ5ee 35 or SC2 34 processes, the travel speed of pulses in the line falls by about 6×. This slowdown yields densities of up to 1.4 and 4.0 Mbit/cm 2 for 250 nm and 120 nm linewidths, respectively, at 100 GHz.…”

“…For instance, SFQ5ee 35 allows for the reliable fabrication of Nb and MoN microstrips and striplines with 500 nm pitch. The more advanced SC2 34 process reduces pitch to 240 nm. Further miniaturization is possible with e-beam lithography 37 .…”

“…When geometric inductance is significant, such as in Nb striplines, the inductance scales non-linearly and must be evaluated at each linewidth individually. Based on experimental measurements 34 , a 250 nm-wide Nb stripline has 0.5 pH/µm, while a 120 nm-wide line has 0.65 pH/µm. When kinetic inductance dominates, such as in the cases of MoN and NbTiN striplines and MoN microstrips, inductance does scale linearly and was found by multiplying known inductance per square values-8 pH/ for MoN striplines and microstrips 41 , and 49 pH/ for NbTiN striplines 36 -by unit length divided by linewidth.…”

“…When kinetic inductance dominates, such as in the cases of MoN and NbTiN striplines and MoN microstrips, inductance does scale linearly and was found by multiplying known inductance per square values-8 pH/ for MoN striplines and microstrips 41 , and 49 pH/ for NbTiN striplines 36 -by unit length divided by linewidth. As for their capacitances, we used recently-published fabrication results 34 . For example, a stripline of 120 nm linewidth has a capacitance of 0.19 fF/µm, depending only on the dielectric material and on the geometry.…”