We investigated the temperature effect on exciton localization in self-organized InAs quantum dots. Quenching energy for excitons in reference quantum well and quantum dots was found to be 2 and 7 meV, respectively. Thermoactivation energy of electron-hole emission through a GaAs barrier in the quantum dots was measured as 46 meV. We observed an unusual decrease of photoluminescence peak full width at half maximum with temperature, suggesting suppression of nonpredominant size quantum dot emissions due to carrier tunneling between nearby dots.
For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube TM ) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.
Electromigration failure kinetic has been studied with resistance evolution versus time of interconnects during degradation. Tests were performed on dual damascene copper lines, issued from the 65 nm technology node, of various widths and lengths. All samples exhibit similar resistance evolution: an initial step, characterized by its height called Rstep, follows a linear kinetic characterized by its slope called Rslope. These two parameters were systematically extracted; Rstep is proportional to the critical volume of a void spanning the whole section of the line, and Rslope to the copper drift velocity. On one hand, the linewidth does not affect these two parameters. On the other hand, Rslope is highly dependent on the line length because of the Blech effect, while Rstep remains constant. Consequently, it was demonstrated that the classical linear function L/TTF=f(jL), where TTF is the time to failure, j is the current density, and L is the line length, used to study the Blech effect in interconnects could be substituted with the linear function RslopeL=f(jL), confirming that Rslope is a suitable parameter to study void growth kinetics. At 300 °C and 2 MA/cm2, a void growth velocity of 1.15×10−8 μm3/s was thus determined on long lines, and an activation energy of 0.95 eV was found. Finally based on the resistance analysis, an explanation is proposed concerning the larger spread observed on the TTF measured on short lines at low current density.
3D VLSI with a CoolCube TM integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm². This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube TM technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization. I-INTRODUCTION: 3D-VLSI sequential processing of stacked devices offers a 3D contact pitch equal to planar contacted gate pitch. Moreover, thanks to the lithography alignment precision depending only on the stacked technology node, the via density reaches 10 8 vias/mm 2 with a 90nm-CPP technology. This 3D contact pitch allows fully leveraging the 3 rd dimension with negligible area penalty due to 3D via or landing pad size compared to packaging solutions as shown in Fig.1 [1] .3DVLSI motivations-Actually, scaling below the 28 nm technology node does not yield substantial cost reductions [2] . Among scaling challenges, the increasing interconnect delay overshadows benefits stemming from costly transistor scaling. 3D VLSI interest has been demonstrated via a Power-Performance-Area benchmark for FPGA applications stacking two layers of 14nm FDSOI technology with W/SiO2 interconnect in between [3] . Dramatic area and Energy Delay Product (EDP) reduction is achieved, with benefits exceeding those of downscaling to the 10 nm node (Figs.2&3). 3DVLSI partitioning at the gate level allows IC performance gain without resorting to scaling thanks to wire length reduction. In parallel, partitioning at the transistor level by stacking n-FET over p-FET (or the opposite) enables the independent optimization of both types of transistors (customized implementation of performance boosters: channel material / substrate orientation / channel and Raised Sources and Drains strain, etc. [6,7] ) with reduced process complexity compared to a planar co-integration. The ultimate example of high performance CMOS at low process cost is the stacking of III-V nFETs above SiGe pFETs [8,9] . These high mobility transistors are well suited for 3DVLSI because their process temperatures are intrinsically low. 3DVLSI partitioning at the transistor level allows performance gain as it facilitates the cointegration of high performance n&p-FETs compared to a coplanar scheme. Finally, 3DVLSI, with its high contact density, is also anticipated as a powerful solution for heterogeneous cointegrations requiring high 3D vias densities such as NEMS with CMOS for gas sensing applications [10, 11] or highly miniaturized imagers [12] . Fig.4 summarizes the three main integration schemes foreseen for ...
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.