14nm FDSOI technology for high speed and energy efficient applications

Weber, O.; Josse, E.; Andrieu, F.; Cros, A.; Richard, Evelyne; Perreau, P.; Baylac, E.; Degors, N.; Gallon, C.; Perrin, E.; Chhun, S.; Petitprez, E.; Delmedico, S.; Simon, Jerome B.; Druais, G.; Lasserre, S.; Mazurier, J.; Guillot, Nicolas; Bernard, E.; Bianchini, Ricardo; Parmigiani, L.; Gerard, X.; Pribat, C.; Gourhant, Olivier; Abbate, F.; Gaumer, C.; Beugin, V.; Gouraud, P.; Maury, P.; Lagrasta, S.; Barge, D.; Loubet, N.; Beneyton, R.; Benoît, Daniel; Zoll, S.; Chapon, J.D.; Babaud, L.; Bidaud, M.; Gregoire, M.; Monget, C.; Le-Gratiet, Bertrand; Brun, P.; Mellier, M.; Pofelski, Alexandre; Clement, L.; Bingert, R.; Puget, S.; Kruck, J.F.; Hoguet, D.; Scheer, P.; Poiroux, T.; Manceau, Jean-Philippe; Rafik, M.; Rideau, D.; Jaud, M.-A.; Lacord, J.; Monsieur, F.; Grenouillet, L.; Vinet, M.; Liu, Quanwei; Doris, B.; Celik, M.; Fetterolf, S.P.; Faynot, O.; Haond, M.

doi:10.1109/vlsit.2014.6894343

Cited by 62 publications

(31 citation statements)

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“…The gate length used for this analysis was the designed length in all cases. The front gate-stack consists of TiN/Hf-based oxide dielectric with equivalent oxide thickness t ox = 1.2 nm, while the silicon film thickness is 7 nm and the BOX thickness is 20 nm [20]. Static characterization was performed in order to obtain the transfer (I d -V g ) and output (I d -V d ) characteristics for front-and back-gate mode of operation and then extract typical MOSFET parameters such as transconductance g m .…”

Section: Resultsmentioning

confidence: 99%

Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

Ioannidis

Theodorou

Karatsori

et al. 2015

IEEE Trans. Electron Devices

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Extensive investigation of the drain-current low-frequency noise in n-channel MOSFETs issued from a 14-nm fully depleted silicon-on-insulator technology node has been carried out. The results demonstrate that the carrier number fluctuation (CNF) with correlated mobility fluctuations (CMFs) model accurately and continuously describes the 1/ f noise from weak to strong inversion, from linear to saturation, and for all the back-bias conditions. It is shown that using only two parameters, i.e., the effective flat-band voltage spectral density S Vfb,eff and CMF factor eff , the CNF/CMF noise model can predict the transistor 1/ f noise level of all channel dimensions and under any bias conditions. Thus, it can be easily used in SPICE noise modeling for circuit simulations.Index Terms-Low-frequency noise (LFN), UTBB fully depleted silicon-on-insulator (FDSOI) MOSFETs.

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Section: Resultsmentioning

confidence: 99%

Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

Ioannidis

Theodorou

Karatsori

et al. 2015

IEEE Trans. Electron Devices

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“…Electrical measurements were performed on n-and p-MOS transistors fabricated using 28 and 14nm FD-SOI CMOS technologies [9,10]. The channel length (L) of the measured devices is the minimum for each technology node, while the widths (W) range between 0.08 to 10 m, and 0.06 to 3 m, for 28nm and 14nm technology nodes, respectively.…”

Section: Methodsmentioning

confidence: 99%

New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

Theodorou

Ioannidis

Haendler

et al. 2015

2015 IEEE International Reliability Physics Symposium

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A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.

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“…The 14nm dual work-function, HighK/Metal Gate-First FDSOI technology has been largely detailed in [1], [3]. The high concentration c-SiGe channel of the pMOS is obtained by Ge condensation.…”

Section: Technology Description and Simulationmentioning

confidence: 99%

TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment

Tavernier

Pereira

Nier

et al. 2015

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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This paper reviews the main challenges for the TCAD of 14nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology performance assessment. Thanks to a multi-scale approach combining extensive electrical characterization and advanced solvers simulations, ensuring deep physical insight, we provide TCAD simulation framework for device layout optimization, strain engineering and device reliability assessment.

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14nm FDSOI technology for high speed and energy efficient applications

Cited by 62 publications

References 0 publications

Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment

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