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Dynamic and partial reconfiguration of Xilinx FPGAs is a well known technique in runtime adaptive system design. With this technique, parts of a configuration can be substituted while other parts stay operative without any disturbance. The advantage is the fact, that the spatial and temporal partitioning can be exploited with the goal to increase performance and to reduce power consumption due to the re-use of chip area. This paper shows a novel methodology for the inclusion of the configuration access port into the data path of a processor core in order to adapt the internal architecture and to re-use this access port as data- sink and source. It is obvious that the chip area, which is utilized by the hardware drivers for the internal configuration access port (ICAP), has to be as small as possible in comparison to the application functionality. Therefore, a hardware design with a small footprint, but with an adequate performance in terms of data throughput, is necessary. This paper presents a fast data path for dynamic and partial reconfiguration data with the advantage of a small footprint on the hardware resources

Current trends in high performance computing show, that the usage of multiprocessor systems on chip are one approach for the requirements of computing intensive applications. The multiprocessor system on chip (MPSoC) approaches often provide a static and homogeneous infrastructure of networked microprocessor on the chip die. A novel idea in this research area is to introduce the dynamic adaptivity of reconfigurable hardware in order to provide a flexible heterogeneous set of processing elements during run-time. This extension of the MPSoC idea by introducing run-time reconfiguration delivers a new degree of freedom for system design as well as for the optimized distribution of computing tasks to the adapted processing cells on the architecture related to the changing application requirements. The "computing in time and space" paradigm and the extension with the new degree of freedom for MPSoCs will be presented with the RAMPSoC approach described in this paper

Operating systems traditionally handle the task scheduling of one or more application instances on a processor like hardware architecture. Novel runtime adaptive hardware exploits the dynamic reconfiguration on FPGAs, where hardware blocks are generated, started and terminated. This is similar to software tasks in well established operating system approaches. The hardware counterparts to the software tasks have to be transferred to the reconfigurable hardware via a configuration access port. This port enables the allocation of hardware blocks on the FPGA. Current reconfigurable hardware, like e.g. Xilinx Virtex 5 provide two internal configuration access ports (ICAPs), where only one of these ports can be accessed at one point of time. In e.g. a multiprocessor system on an FPGA, it can happen that multiple instances try to access these ports simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled by a special purpose operating system running on an embedded processor. This special purpose operating system, called CAPOS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the service of priority-based access scheduling, hardware task mapping and resource management

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Multi-processor architectures are a promising solution to provide the required computational performance for applications in the area of high performance computing. Multi- and many-core Systems-on-Chip offer the possibility to host an application, partitioned in a number of tasks, on the different cores on one silicon die. Unfortunately, a partitioning of the tasks near to the performance optimum is the challenge in this domain and often a show-stopper for the success story of multi- and many-core hardware. The missing feature of these architectures is runtime adaptivity of the underlying hardware, which offers to tailor the hardware to the application in order to meet the task mapping process coming from top-down development. Especially, this Meet-in-the- Middle solution offers the novel hardware and software approach of RAMPSoC, which is described in this paper

Synthetic aperture radar (SAR) is a well-known imaging technique and most commonly used up to the microwave frequency spectrum (below 30 GHz) which provides spatial resolution in the sub-m range. To enhance the resolution, higher frequency spectra such as millimeter-wave (mmWave) and terahertz (THz) regions are being investigated. The mmWave and THz spectral ranges extend the SAR applications to nondestructive testing (NDT), material characterization, and sub-mm resolution imaging. However, the higher frequency spectrum suffers from higher path loss and potentially higher atmospheric absorption that limits the propagation distance. Nevertheless, the mmWave/THz spectrum is suitable for short-range applications such as indoor room profiling. From theoretical analysis, it can be summarized that the higher frequency spectrum provides better resolution but a comparative study on the impact on the image quality of the frequency spectrum ranging from GHz to THz has not been presented. Besides, as of the hardware complexity of the THz devices, the optimum range of the spectrum is always under investigation. The optimum range is defined where no strong improvements in the image quality are achievable with further increases in the frequency spectrum. Therefore, this paper presents an overview of electronics-based imaging using the SAR technique for the frequency spectrum ranging from GHz to THz with the focus on NDT and high-resolution imaging. Seven frequency bands: 5-10 GHz, 68-92 GHz, 75-110 GHz, 0.122-0.168 THz, 0.22-0.33 THz, 0.325-0.5 THz, and 0.85-1.1 THz are selected for a comparative analysis. The results are presented for 2D and 3D imaging using the backprojection algorithm. Additionally, state-of-the-art imaging based on SAR technique with electronics transceiver modules has only been demonstrated up to the sub-0.75 THz, whereas in this paper the spectrum up to 1.1 THz has been addressed.INDEX TERMS GHz and THz comparison, high-resolution imaging, non-destructive testing, synthetic aperture radar, terahertz imaging, radar imaging.This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.