Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs

Abstract

Dynamic and partial reconfiguration of Xilinx FPGAs is a well known technique in runtime adaptive system design. With this technique, parts of a configuration can be substituted while other parts stay operative without any disturbance. The advantage is the fact, that the spatial and temporal partitioning can be exploited with the goal to increase performance and to reduce power consumption due to the re-use of chip area. This paper shows a novel methodology for the inclusion of the configuration access port into the data path of a processor core in order to adapt the internal architecture and to re-use this access port as data- sink and source. It is obvious that the chip area, which is utilized by the hardware drivers for the internal configuration access port (ICAP), has to be as small as possible in comparison to the application functionality. Therefore, a hardware design with a small footprint, but with an adequate performance in terms of data throughput, is necessary. This paper presents a fast data path for dynamic and partial reconfiguration data with the advantage of a small footprint on the hardware resources

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

“…We could potentially get similar values as the theoretical ones, by using a FSM as the configuration controller and downloading the configuration bitstream using "bit-parallel" mode. Furthermore, we are investigating the existing ICAP architectures and design techniques used in [16,18,25,27] and planning to explore ways to design and incorporate similar techniques, to enhance the reconfiguration process.…”

“…There is several existing research work on enhancing the ICAP architecture in order to accelerate the reconfiguration flow [16,18,25,27]. We are currently investigating these architectures and design techniques, and planning to explore ways to design and incorporate similar techniques, which could potentially reduce the reconfiguration time overhead of our current reconfigurable hardware designs.…”

The Paramountcy of Reconfigurable Computing

“…An interesting project proposes to use cache space isolation techniques to avoid cache contention for hard real-time tasks running on multicores with shared caches 274 . Dynamic reconfiguration capabilities of current reconfigurable devices can create an additional dimension in the temporal domain 226,238,263,275 . During the design space exploration phase, overheads associated with reconfiguration and hardware/software interfacing need to be evaluated carefully in order to harvest the full potential of dynamic reconfiguration 276 .…”

“…The algorithmic complexity turns from O(n2) into O(n)3. In a similar manner, other well-known algorithmic methods can be transformed to explore parallelism and locality, like in dynamic programming as presented in 275 . The combination of these effects leads to massive speed-up and massive saving of energy (see section 19.5.4).…”

“…It is triggered via handshake by the arrival of the data item, not needing an instruction to call it. Not looking at dynamically reconfigurable systems (only for advanced courses 275 ) we see, that reconfigurable fabrics don't perform any instruction sequencing at run time.…”