Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

Abstract

With the advancement of mobile and embedded devices, many applications such as data mining have found their way into these devices. These devices consist of various design constraints including stringent area and power limitations, high speed-performance, reduced cost, and time-to-market requirements. Also, applications running on mobile devices are becoming more complex requiring significant processing power. Our previous analysis illustrated that FPGA-based dynamic reconfigurable systems are currently the best avenue to overcome these challenges. In this research work, we introduce efficient reconfigurable hardware architecture for principal component analysis (PCA), a widely used dimensionality reduction technique in data mining. For mobile applications such as signature verification and handwritten analysis, PCA is applied initially to reduce the dimensionality of the data, followed by similarity measure. Experiments are performed, using a handwritten analysis application together with a benchmark dataset, to evaluate and illustrate the feasibility, efficiency, and flexibility of reconfigurable hardware for data mining applications. Our hardware designs are generic, parameterized, and scalable. Furthermore, our partial and dynamic reconfigurable hardware design achieved 79 times speedup compared to its software counterpart, and 71% space saving compared to its static reconfigurable hardware design.

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

“…This difference was further investigated, analyzed, and detailed in [21], [38]. From our previous work [20], [21], it was observed that the partial reconfiguration time overhead is in the range of milliseconds for the bit files of similar sizes. All these facts and our previous work [20], [21], [40], [49] illustrate that this difference between theoretical and experimental values for reconfiguration time overhead is quite normal.…”

“…From our previous work on dynamic and partial reconfigurable hardware architectures for data mining/analytics applications [20], [21], [40], [49] on embedded devices, it was observed that the percentage of reconfiguration time was amortized and decreased, as the computation complexity (i.e., the number of iterations/computations) increases as well as the size of the data increases; however, the percentage of reconfiguration time was significant for lower number of iterations/computations and smaller data sizes [20], [21]. Conversely, for our DRH designs for cryptographic algorithms, the percentage of reconfiguration time remains almost the same for each configuration.…”

“…From our previous work on dynamic and partial reconfigurable hardware architectures for data mining/analytics on embedded devices [20], [21], [40], [49], it was observed that the DRH designs and SRH designs achieved similar speedups, when considering the execution times for individual tasks/operations. This behavior is similar to the speedup results of our DRH and SRH for SPECK and SIMON algorithms, presented in this paper.…”

“…Furthermore, with the dynamic and partial reconfiguration capabilities, parts of the chip/FPGA can be modified, while other parts are still operational. This in turn leads to significant space savings on chip for complex embedded applications [20], [21]. In addition, with FPGAs, time-to-market is reduced, since FPGAs are pre-fabricated, hence, immediately available.…”

Ultra-Compact Balanced Multiband Fully Reconfigurable Bandstop Filter

“…Moreover, the reconfigurable circuitry is getting much attention recently in electronic industry, whether it is a digital application such as embedded system, data mining etc. [5,6] or it is an RF frontend application such as amplifier, antenna etc. [7,8].…”