2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW) 2010
DOI: 10.1109/ipdpsw.2010.5470800
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High performance reconfigurable multi-processor-based computing on FPGAs

Abstract: Multi-processor architectures are a promising solution to provide the required computational performance for applications in the area of high performance computing. Multi- and many-core Systems-on-Chip offer the possibility to host an application, partitioned in a number of tasks, on the different cores on one silicon die. Unfortunately, a partitioning of the tasks near to the performance optimum is the challenge in this domain and often a show-stopper for the success story of multi- and many-core hardware. Th… Show more

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Cited by 24 publications
(18 citation statements)
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References 12 publications
(17 reference statements)
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“…A construction methodology perspective may concentrate on any level of abstraction defined within this process: Recent literature on VHDL programming perspectives describe a number of distinct methodologies. All of these methodologies can be grouped into three mainstreams that differ in design philosophy [26][27][28][29]: a. Top-down approach (behavioural)…”
Section: A Construction Methodology Perspectivementioning
confidence: 99%
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“…A construction methodology perspective may concentrate on any level of abstraction defined within this process: Recent literature on VHDL programming perspectives describe a number of distinct methodologies. All of these methodologies can be grouped into three mainstreams that differ in design philosophy [26][27][28][29]: a. Top-down approach (behavioural)…”
Section: A Construction Methodology Perspectivementioning
confidence: 99%
“…The complexity of designed ICs favoured the development of new design methodologies based on abstraction. Three strategies may be distinguished in design methodologies [26][27][28][29]: -Top-Down, proceeds hierarchically from an abstract level to a more detailed one by successive decomposition into subsystems. With top-down design, the circuit can first be modelled by making a behavioural model.…”
Section: A Modelling Perspectivementioning
confidence: 99%
“…The work in [16] proposes a hardware OS, called CAP-OS, that uses run-time scheduling, task mapping, and resource management on a run-time reconfigurable multiprocessor system. The authors in [17] proposed to use the RAMPSOC with two schedulers: a static scheduler to generate a task graph and assign resources and a dynamic scheduler that uses the generated task graph produced by the static scheduler. A deadline constraint for the entire graph is imposed instead of individual tasks.…”
Section: Related Workmentioning
confidence: 99%
“…(2) ReadyQ =findAvailableTasks(DFGs)//no dependencies (3) while there are unscheduled tasks do (4) if (Reuse = true) (5) for all tasks in ReadyQ do (6) PRR# = FindAvailablePRR(task) (7) if (PRR#) then (8) ts=t (9) for all p in PredecessorOf(task) (10) ts=max(ts, tps + tpl) (11) end for (12) remove task from ReadyQ (13) end if (14) end for (15) else /⋆Reuse = false⋆/ (16) for all tasks in ReadyQ do (17) PRR# = findEmptyPRR(task) (18) if (PRR# and Reconfiguration) then (19) ts=t+trs (20) for all p in PredecessorOf(task) (21) ts=max(ts, tps + tpl) (22) end for (23) Remove task from ReadyQ (24) end if (25) end for (26) end if (27) ReadyQ=CheckforAvailableTasks /⋆ dependencies met ⋆/ (28) end while Algorithm 1: Pseudo-code for RCOffline.…”
Section: Rcofflinementioning
confidence: 99%
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