Runtime adaptive multi-processor system-on-chip: RAMPSoC

Göhringer, Diana; Hübner, Michael; Schatz, Volker; Becker, Jürgen

doi:10.1109/ipdps.2008.4536503

Cited by 42 publications

(23 citation statements)

References 10 publications

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“…Authors in [14] demonstrate that combination of multi-core processor and reconfigurable instruction set extensions creates multi-level parallelism for high performance system. Authors in [15] suggest one or more accelerators are loosely attached to processors in MPSoC platform. Here, the accelerator is configured partially and dynamically so that hardware can be adapted during run-time.…”

Section: Related Workmentioning

confidence: 99%

A platform for multi reconfigurable instruction set processor system on chip (MRPSoC)

Soleymanpour

Mohammadi

2013

The 17th CSI International Symposium on Computer Architecture &Amp; Digital Systems (CADS 2013)

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The rapid growth of computation requirements has caused traditional platforms to become deficient in providing the desired conditions of evolving applications. Multiprocessor system on chip (MPSoC) and application specific instruction set (ASIP) are two interesting solutions that can be employed to attain optimal throughput. This paper describes a novel platform for MPSoC adapting processing elements to specific application by means of reconfigurable hardware. The proposed platform consists of multi reconfigurable instruction set processors System on Chip (MRPSoC). The platform can run applications in parallel and enhance performance due to its reconfigurable function unit (RFU), while retaining programmability. Also, we introduce a methodology along with MRPSoC to efficiently use the platform. In MRPSoC, custom instructions (CIs) of critical portions of the code are executed on RFU. To verify the efficiency of our platform, we run applications such as multimedia, networking and encryption. Finally, we show that the completion time of applications is improved by 40.90% on average compared to homogeneous MPSoCs.

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Section: Related Workmentioning

confidence: 99%

A platform for multi reconfigurable instruction set processor system on chip (MRPSoC)

Soleymanpour

Mohammadi

2013

The 17th CSI International Symposium on Computer Architecture &Amp; Digital Systems (CADS 2013)

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“…The RAMSoC [4] is an interesting project, where are addressed the two main drawbacks of traditional approaches. The first one is the necessity to find a trade-off between homogeneous and application-specific MPSoC.…”

Section: Related Workmentioning

confidence: 99%

Rapid Application Development on Multi-processor Reconfigurable Systems

Diguet

Gogniat

2010

2010 International Conference on Field Programmable Logic and Applications

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Abstract-Considering the ability to perform multi-processor architecture systems on FPGA, partial reconguration is an opportunity to improve weak soft-core performances by specializing coprocessors according to context-dependent application needs. But at the application level, there is a need for straightforward programming models that allow applications to be easily mapped on an ad hoc architecture without tedious rewriting, while at the same time ensuring efcient production code. In this paper we describe two programming libraries XTask and XFunc, which are written in C and rely on a recongurable MPSoC architecture model (XPSoC) and on HW/SW libraries of standard functions that can be easily used by means of HW independent API. Finally, we demonstrate the XPSoC methodology, with the design of a self-adaptive image encoding system including runtime conguration decisions.

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“…The innovation in our embedded MPSoC called RAMPSoC [9] is the utilization of partial dynamic reconfiguration for the on-demand adaptation to application requirements. With common off-the-shelf MPSoCs, such as [24,7], this flexibility, high performance and low power consumption is not feasible for such a wide field of applications [31].…”

Section: Motivation and Approach For A 2d-systemmentioning

confidence: 99%

“…Then the approach of extending the 1D-system architecture to a 2D-system will be described. The 2D-system architecture is a runtime adaptive multiprocessor System-on-Chip (MPSoC), called RAMPSoC [9]. It is heterogeneous in the sense, that it supports not only different type of processors but also standalone hardware functions.…”

mentioning

confidence: 99%

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture

Braun

Göhringer

Perschke

et al. 2008

J Real-Time Image Proc

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Fine grained reconfigurable architectures, like Xilinx field programmable gate arrays (FPGAs) provide a high flexibility through runtime re-programming, called dynamic and partial reconfiguration. This feature allows for runtime adaptation of the system architecture and behavior configured on the FPGA. The exploitation of this feature enables to load video image processing algorithms ondemand in order to adapt the configuration in correspondence to the changing requirements of the application depending on the image content. For high resolution sensor images, this novel computing paradigm can provide a huge benefit in power reduction and performance gain for actual and future embedded electronic systems. This paper presents a two dimensional system approach exploiting dynamic and partial reconfiguration in order to adapt the system architecture to the actual requirements of image processing applications. The methodology of runtime reconfiguration can be exploited beneficially for highly adaptive multiprocessor systems. Such systems, different from the traditional static approach for multi-and manycore architectures have the advantage, for providing computational performance directly linked to the requirements of the application. The architecture presented in this paper allows for adapting the processing elements as well as the communication infrastructure which is a novel 2D switchbased Network-on-Chip. The presented approach follows and extends the actual trend in computer science of using many-and multi-core processors for bridging the gap between required computation performance for future application in the field of image processing.

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Runtime adaptive multi-processor system-on-chip: RAMPSoC

Cited by 42 publications

References 10 publications

A platform for multi reconfigurable instruction set processor system on chip (MRPSoC)

A platform for multi reconfigurable instruction set processor system on chip (MRPSoC)

Rapid Application Development on Multi-processor Reconfigurable Systems

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture

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