A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip

Göhringer, Diana; Hübner, Michael; Benz, Michael; Becker, Jürgen

doi:10.1109/fccm.2010.47

Cited by 19 publications

(18 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A design methodology for the application partitioning of reconfigurable MPSoCs is presented in [6]. The methodology supports the partitioning of an application between several processing elements (SW/SW partitioning) at the function level, as well as, HW/SW partitioning.…”

Section: Related Workmentioning

confidence: 99%

“…The approach taken in [6] is similar to our work with regard to addressing application partitioning on the coarse function level. However, in our approach we utilize a different set of input data.…”

Section: Related Workmentioning

confidence: 99%

“…However, in our approach we utilize a different set of input data. Instead of the common call graph, utilized by [6], we employ the Quantitative Data Usage (QDU) graph [7] as the primary reference for partitioning the application. The information about the data communication between functions, represented by this graph, is automatically determined by our advanced profiling toolset.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Profile-guided application partitioning for heterogeneous reconfigurable platforms

Ostadzadeh

Meeuws

Ashraf

et al. 2012

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)

View full text Add to dashboard Cite

Abstract-The increased complexity of programming heterogeneous reconfigurable platforms requires a thorough understanding of application behavior, for which developers need sophisticated analysis tools. One particular problem, which severely limits the performance gain of running applications on these platforms, is the inappropriateness of the kernels mapped onto the reconfigurable fabrics. Efficient porting of legacy applications to these emerging heterogeneous platforms demands code tuning considering several critical points, such as, proper kernel size and small memory communication overhead. Detailed profiling information is thus vital for an efficient HW/SW co-design. To facilitate addressing these issues, we developed the Q 2 profiling framework. It consists of two parts: an advanced memory access profiling toolset that provides detailed information on the run-time memory access patterns of an application and a statistical modeling framework that makes predictions for resources, early in the design phase, based on software metrics. The code optimizations triggered by careful analysis of the profiling information is used to tailor existing applications for heterogeneous reconfigurable platforms. In this paper, we examine a real application in detail to show the potential of the proposed profiling framework. Experimental results show that a speedup of 1.3× is achieved by accelerating a merged kernel of four critical functions in the application.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Profile-guided application partitioning for heterogeneous reconfigurable platforms

Ostadzadeh

Meeuws

Ashraf

et al. 2012

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)

View full text Add to dashboard Cite

show abstract

“…Pouchet et al [2013] proposed a framework to optimize data reuse for a class of programs through which the data communication overhead was reduced. In [Goringer et al, 2010], the authors present the partitioning of an application between several processing elements (SW/SW partitioning) at the function-level, as well as HW/SW partitioning utilizing some profiling information. The work in extended the QUAD toolset to provide the information about the unique data values involved in inter-function data-communication.…”

Section: Software Level Optimizationmentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

View full text Add to dashboard Cite

Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

show abstract

“…Several tool flows have been provided that support mapping applications onto reconfigurable architectures. Automated partitioning and synthesis is, for example, enabled by Synopsys' Certify or the flow reported in [10]. Their result, however, is a static, single-mode embedded system and, thus, they are not able to exploit the flexibility of dynamically reconfigurable hardware at run-time.…”

Section: Introductionmentioning

confidence: 99%

Symbolic design space exploration for multi-mode reconfigurable systems

Wildermann

Reimann

Ziener

et al. 2011

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

View full text Add to dashboard Cite

Abstract-In today's complex embedded systems not all applications are running all the time, but depend on the operational mode. By incorporating knowledge about the temporal behavior of such multi-mode systems, it is possible to share hardware by means of partial reconfiguration, and thus, reduce costs and improve performance. In this paper, we specify the temporal behavior of the functionality by applying known models based on state machines. In addition, we introduce an architectural model that allows to express the characteristics of nowadays partially reconfigurable architectures, focusing on FPGAs. We develop a symbolic encoding of this novel system specification, which allows to perform a unified system synthesis for allocation, binding, placement of partially reconfigurable modules, and routing the on-chip communication. The proposed encoding enables the use of sophisticated optimization techniques, coupling a SAT solver with a Multi-objective Evolutionary Algorithm. The proposed methodology is highly applicable for building multi-mode systems on advanced reconfigurable technology. We demonstrate this by experiments on test-cases from the image processing domain applying state-of-the-art technology. The results show the superiority of the presented approach in terms of run-time and quality of the found solutions compared to existing system synthesis approaches.

show abstract

A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip

Cited by 19 publications

References 5 publications

Profile-guided application partitioning for heterogeneous reconfigurable platforms

Profile-guided application partitioning for heterogeneous reconfigurable platforms

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Symbolic design space exploration for multi-mode reconfigurable systems

Contact Info

Product

Resources

About