Against a backdrop of the latest ITRS predictions for CMOS junctions, we compare methods for dopant introduction and activation, methods for making contact to these regions, and methods for measurement of material and device properties. As activation without diffusion (sub-melt laser, capacitor discharge flash, or solid phase epitaxy) becomes more feasible, the burden on Xj, Rsh and abruptness falls on the implanters, and the process margin appears slim, opening the door for other methods of doping. For contact resistance, a major component of transistor parasitics, we find that either a move to a different substrate, or from a single midgap silicide to two band-edge metals/silicides can be quite beneficial. Through the use of simple test structures, we describe a means of extracting each component of the parasitic resistance, facilitating development of materials for CMOS junctions.
Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MOSFET integrations. These device architectures can improve performance such as better short channel performance and reduced leakage. In I VKt) .=vmcar(wmt) 3 .os D#*.A"C. ("rn, Fig 8: Electrostatic potential and Electron density variation Fig 9 A single transitor square la 98
AbstractPower consumption including leakage current is becoming one of the most important limiting factors in VLSI, especially in the sub-65nm technologies. While technologies are facing multiple challenges in scaling, there have been successful developments on reduction of power consumption and leakage current in circuit and system design techniques based on the cooperation between two traditionally separated technical fields -technology and design. The benefits of separate gate access capability of DG-FDSOI technology on supporting these kinds of cooperation techniques have been addressed together with the impact on circuit designs which take advantages of this technology.
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