Directed self-assembly (DSA) of lamellar phase block-co-polymers (BCPs) can be used to form nanoscale line-space patterns. However, exploiting the potential of this process for circuit relevant patterning continues to be a major challenge. In this work, we propose a way to impart two-dimensional pattern information in graphoepitaxy-based lamellar phase DSA processes by utilizing the interactions of the BCP with the template pattern. The image formation mechanism is explained through the use of Monte Carlo simulations. Circuit patterns consisting of the active region of Si FinFET transistors, referred to as Si "fins", were fabricated to demonstrate the applicability of this technique to the formation of complex patterns. The quality of the Si fin features produced by this process was validated by demonstrating the first functional DSA-patterned FinFET devices with 29 nm-pitch fins.

We describe a liner' for Cu-Damascene multilevcl ULSI interconnects, which satisfies all the important requirements for a high performance and reliable Cu interconnect technology. This liner is implemented in the first manufacturing process to produce and ship CMOS chips with Cu interconnects'. The liner is a bilayer from a family of hcp/bcc-TaN followed by bcc-Ta (a-Ta), deposited sequentially in a single PVD chamber from a pure Ta target, using Ar and Nz sputtering gases. This bilayer simultaneously maximizes adhesion to the interlevel dielectric and the Cu fill, and has very low in-plane resistivity (-30-60 M-cm, depending on TaN/Ta thicknesses). These qualities produce high-yield, highly reliable, and electromigration-redundant Cu interconnects. Introduction Many liners have been implemented in experimental Cu integration schemes. The family of Ta-based compounds has emerged prominently. Ta (P-phase) was first shown to be an excellent Cu diffusion barrier in 1986 by Hu et d 3 . It was since found4 that a low background level (e.g. < l o 7 Torr) of O2 or H 2 0 was responsible for decreasing Cu diffusivity through Ta grain boundaries. (Presumably, current studies that fmd reduced Ta barrier performance stem fiom the low base pressures of modem PVD systems, and could be helped by a controlled leak of 02.) Such a P-Ta(0) barrier was used in the first multilevel Cu integration in polyimide ILD', due to its optimal adhesion to the materials used6. For dualDamascene integration in Si022 however (see fig. 1 .), Ta and Ta2N7 lack adequate adhesion to SO2, whereas TaN/SiO2 adhesion is excellent ( fig. 2). On the other hand, Cu/TaN adhesion is relatively poor. In fact, the liner/ILD and Cdliner adhesion have conflicting dependencies on N% in TaN,. We believe it is essential to maximize adhesion at all interfaces, especially the Cu/liner one. This is both to resist delamination during processing or thermal stressing, and for electromigration resistance in fine Cu lines, where interfacial and surface migration play a large role*. As confirmed elsewhere', Cu E-M lifetimes are lower when against a TaN vs. a Ta liner. Unlike CdTaN, /W, and /TiN, the CdTa interface exhibits high wetting" and atomic-scale mixing". This occurs without alloying, which would consume Cu atoms. The Cu/Ta interface is thus uniquely optimal among the commonly studied candidates.Another essential liner quality which has not been addressed generally elsewhere and which is lacking in TaN or TiN, is the capacity for current-strapping (electromigration rcdundancy) by a suitably thin liner. In thc event of Cu defects or elcctromigration wearout, a propcr liner should prevent or dclay open-circuit failurc, cvcn at maximum rated currcnt concentrated in the liner. Such rcdundancy is achieved by the TiAh alloy ovedunder cladding in our AI(Cu) interconnects, and is a reliability requirement for our Cu interconnccts as well. DiscussiodData Our evaluation factors for designing a Cu Damascenc liner are shown in Table I, with results from screening of many candidat...

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Quantum computers built with superconducting artificial atoms already stretch the limits of their classical counterparts. While the lowest energy states of these artificial atoms serve as the qubit basis, the higher levels are responsible for both a host of attractive gate schemes as well as generating undesired interactions. In particular, when coupling these atoms to generate entanglement, the higher levels cause shifts in the computational levels that leads to unwanted ZZ quantum crosstalk.Here, we present a novel technique to manipulate the energy levels and mitigate this crosstalk via a simultaneous AC Stark effect on coupled qubits. This breaks a fundamental deadlock between qubit-qubit coupling and crosstalk, leading to a 90ns CNOT with a gate error of (0.19 ± 0.02) % and the demonstration of a novel CZ gate with fixed-coupling single-junction transmon qubits. Furthermore, we show a definitive improvement in circuit performance with crosstalk cancellation over seven qubits, demonstrating the scalability of the technique. This work paves the way for superconducting hardware with faster gates and greatly improved multi-qubit circuit fidelities.

Improving two-qubit gate performance and suppressing crosstalk are major, but often competing, challenges to achieving scalable quantum computation. In particular, increasing the coupling to realize faster gates has been intrinsically linked to enhanced crosstalk due to unwanted two-qubit terms in the Hamiltonian. Here, we demonstrate a novel coupling architecture for transmon qubits that circumvents the standard relationship between desired and undesired interaction rates. Using two fixed frequency coupling elements to tune the dressed level spacings, we demonstrate an intrinsic suppression of the static ZZ, while maintaining large effective coupling rates. Our architecture reveals no observable degradation of qubit coherence (T1, T2 > 100 µs) and, over a factor of 6 improvement in the ratio of desired to undesired coupling. Using the cross-resonance interaction we demonstrate a 180 ns single-pulse CNOT gate, and measure a CNOT fidelity of 99.77(2)% from interleaved randomized benchmarking.

Highly scaled FinFET SRAM cells, of area down to 0.128μm 2 , were fabricated using high-κ dielectric and a single metal gate to demonstrate cell size scalability and to investigate V t variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce V t variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187μm 2 cell, at V d = 0.6 V, a static noise margin (SNM) of 95 mV was obtained and stable read/write operations were verified from N-curve measurements. σV t of transistors in 0.187μm 2 cells was measured with and without channel doping and the result was summarized in the Pelgrom plot. With the 22 nm node design rule, FinFET SRAM cell layouts were compared against planar-FET SRAM cell layouts. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a planar-FET SRAM cell, which would have higher σV t mainly caused by heavy doping into the channel region.

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