Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

Bangsaruntip, Sarunya; Balakrishnan, Karthik; Cheng, Szu-Lin; Chang, Josephine; Brink, Markus; Lauer, Isaac; Bruce, Robert L.; Engelmann, Sebastian; Pyzyna, A.; Cohen, Guy; Gignac, Lynne; Breslin, Chris; Newbury, J.; Klaus, D.; Majumdar, Amlan; Sleight, J.W.; Guillorn, Michael A.

doi:10.1109/iedm.2013.6724667

Cited by 85 publications

(60 citation statements)

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“…Gate-all-around (GAA) FETs offer the best potential solution to electrostatic control, and can be implemented in a lateral (with one or more lateral wires which are vertically stacked) [94,95] or a vertical configuration [96,97]. The lateral nanowire FETs are closer to FinFETs in terms of processing, circuit design, as well as footprint constraints.…”

Section: Common Challenges: Less Lateral Space Leftmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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Section: Common Challenges: Less Lateral Space Leftmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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“…For the purpose of applying the SNWT structures into the fabrication process flow of conventional bulk-silicon (Si) FinFETs for mass production, the fabrication technologies of GAA-SNWTs are necessary to be compatible with current state-of-the-art integration technology [4]. However, the traditional approach to fabricate GAA-SNWTs is to form and release the NW channels in the initial step of the transistor's fabrication and it causes a series of integration challenges [5,6,7]. The nanoscale NWs suspended on source/ drain (S/D) pads are vulnerable to be broken during the gate etch and S/D engineering.…”

Section: Introductionmentioning

confidence: 99%

“…On the normal Si substrate, the fin is patterning with general spacer-transfer lithography (STL) and it forms a sea of fins with the same pattern across whole the wafer. The landing pads with large geometry sizes, which are generally used for physical supporting the suspended NWs in previous reports [5,6,7], are removed from this process. A special etch process for a notched fin is developed for the formation of NW channels in later steps.…”

Section: Introductionmentioning

confidence: 99%

Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate

Hong

2015

IEICE Electron. Express

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For the first time, a Gate-All-Around (GAA) Silicon Nanowire Transistor (SNWT) with one special nanowire channel-last (NCL) process technology on silicon (Si) substrate is reported. Different from the traditional approach that the nanowire channels are formed and released at the initial steps of the process flow, the NCL process features the release of nanowire channels in high-k/metal gate-last process during the integration of conventional bulk-Si FinFET. It provides a stable way for the introduction of nanowire transistors in the FinFETs process for mass productions. The fabricated n-type transistors with the effective nanowire diameter (D NW ) of 12 nm∼17 nm and the gate length of 100 nm demonstrated excellent subthreshold characteristics (subthreshold swing = 64 mV/V and drain induced barrier lowering = 24 mV/V). Meanwhile, it's found that the H 2 baking process as well as the optimized interface gate oxidation on NW channels greatly improved the device's SS and off-current parameters.

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“…Though modern MOS device technology may rely on ion-implantation free approaches [26,27], applications of ion implantation are expanding over areas of quantum information processing [28,29] and photovoltaics [30,31]. Plasma immersion ion implantation enables fabrication of 3D transistor architectures [32,33] required for scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) and is technologically more convenient for the fabrication of shallow pn-junctions.…”

Section: à3mentioning

confidence: 99%

Ion-Beam-Induced Defects in CMOS Technology: Methods of Study

Fedorenko¹

2017

Ion Implantation - Research and Application

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Ion implantation is a nonequilibrium doping technique, which introduces impurity atoms into a solid regardless of thermodynamic considerations. The formation of metastable alloys above the solubility limit, minimized contribution of lateral diffusion processes in device fabrication, and possibility to reach high concentrations of doping impurities can be considered as distinct advantages of ion implantation. Due to excellent controllability, uniformity, and the dose insensitive relative accuracy ion implantation has grown to be the principal doping technology used in the manufacturing of integrated circuits. Originally developed from particle accelerator technology, ion implanters operate in the energy range from tens eV to several MeV (corresponding to a few nms to several microns in depth range). Ion implantation introduces point defects in solids. Very minute concentrations of defects and impurities in semiconductors drastically alter their electrical and optical properties. This chapter presents methods of defect spectroscopy to study the defect origin and characterize the defect density of states in thin film and semiconductor interfaces. The methods considered are positron annihilation spectroscopy, electron spin resonance, and approaches for electrical characterization of semiconductor devices.

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Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

Cited by 85 publications

References 1 publication

The Challenges of Advanced CMOS Process from 2D to 3D

The Challenges of Advanced CMOS Process from 2D to 3D

Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate

Ion-Beam-Induced Defects in CMOS Technology: Methods of Study

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