Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate

Abstract

For the first time, a Gate-All-Around (GAA) Silicon Nanowire Transistor (SNWT) with one special nanowire channel-last (NCL) process technology on silicon (Si) substrate is reported. Different from the traditional approach that the nanowire channels are formed and released at the initial steps of the process flow, the NCL process features the release of nanowire channels in high-k/metal gate-last process during the integration of conventional bulk-Si FinFET. It provides a stable way for the introduction of nanowire transistors in the FinFETs process for mass productions. The fabricated n-type transistors with the effective nanowire diameter (D NW ) of 12 nm∼17 nm and the gate length of 100 nm demonstrated excellent subthreshold characteristics (subthreshold swing = 64 mV/V and drain induced barrier lowering = 24 mV/V). Meanwhile, it's found that the H 2 baking process as well as the optimized interface gate oxidation on NW channels greatly improved the device's SS and off-current parameters.

Steep Subthreshold Swing n- and p-Channel Operation of Bendable Feedback Field-Effect Transistors with p+–i–n+ Nanowires by Dual-Top-Gate Voltage Modulation

“…Table shows the comparison between the electrical characteristics of our bendable NW FBFETs and other standard Si and Si NW CMOS-technology devices constructed on bulk or SOI substrates. − The I on and I on / I off values of our device are comparable to (and competitive with) those of wafer-based Si or Si NW device counterparts. Moreover, one of our devices exhibits a very low SS point value of ∼10 mV/dec, which cannot be achieved in standard Si and Si NW CMOS-technology devices.…”

New structure transistors for advanced technology node CMOS ICs

“…Early fabrication approaches for the GAA device used an NW-first scheme based on selective etching and oxidation between two large SD landing pads, but this approach is not compatible with existing FinFET processes [ 29 ]. An NW-last scheme in a replacement metal gate (RMG) module based on an HKMG FinFET was proposed by Ma at IMECAS in 2015 [ 30 ], where the Si NW was released by dilute HF etching with the support of the spacers and zero-level interlayer dielectric. Stacked Si NW-last GAAFETs with GeSi/Si superlattice stacks offer a more feasible solution and the gate control capabilities of the transistor with stacked Si NW diameters of 8 nm in the RMG module realized by a selective release process were first demonstrated by IMEC in 2016, based on their bulk Si HKMG-FinFET process [ 31 ].…”