Steep Subthreshold Swing n- and p-Channel Operation of Bendable Feedback Field-Effect Transistors with p<sup>+</sup>–i–n<sup>+</sup> Nanowires by Dual-Top-Gate Voltage Modulation

Kim

2017

Sci Rep

Self Cite

In this study, we demonstrate the static random access memory (SRAM) characteristics generated by weak impact ionization in bendable field-effect transistors (FETs) with n+-p-n+ silicon nanowire (SiNW) channels. Our bendable SiNW FETs show not only superior switching characteristics such as an on/off current ratio of ~105 and steep subthreshold swing (~5 mV/dec) but also reliable SRAM characteristics. The SRAM characteristics originate from the positive feedback loops in the SiNW FETs generated by weak impact ionization. This paper describes in detail the operating mechanism of our device and demonstrates the potential of bendable SiNW FETs for future SRAM applications.

Section: Introductionmentioning

confidence: 99%

Memory characteristics of silicon nanowire transistors generated by weak impact ionization

Kim

2017

Sci Rep

Self Cite

“…Finally, the potential barriers decrease exponentially in a short time as a result of the repeated injection of charge carriers. This repeated mutual interaction phenomenon is considered as a positive feedback loop that causes the abrupt flow of the current in the channel region . Hence, as shown in Figure a, our transistor turns on very quickly at V G2 = 0.5 V owing to the positive feedback loop triggered by injected electrons, maintains the on state at V G2 = 0 V, and turns off at V G2 = −0.4 V under the reverse sweeping.…”

Section: Resultsmentioning

confidence: 89%

Switchable‐Memory Operation of Silicon Nanowire Transistor

Kim

Cho

et al. 2018

Adv Elect Materials

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of conventional memory are advantages of SRAM and DRAM over new alternatives. Therefore, they will retain their mainstream position in the memory industry for the foreseeable future. Technologies have been proposed to solve the aforementioned limitations of traditional memory devices, such as removing the storage capacitor of DRAM [16,17] and reducing the number of transistors of SRAM. [18] In this study, we demonstrate a switchable-memory transistor with a p + -i-n + doped silicon nanowire whose fabrication process is fully compatible with silicon-based complementary metal-oxide semiconductor (CMOS) technology. The outstanding memory characteristics originate from the positive feedback loop in the intrinsic channel. Notably, our single device not only reduces the number of transistors (constituting a single SRAM cell) in the memory device but also operates the switching function. This is one of the novel strengths of our switchable-memory device for future electronics, as conventional memory devices only provide the function of data storage. The decrease in the number of transistors and the operation of multiple functions can be beneficial for scaling the memory device with regard to the total chip size and power consumption. Hence, we propose a feedback field-effect transistor (FET) with a dual top-gated silicon nanowire channel to enable the switching and memory functions in a single transistor. Results and DiscussionWe demonstrate the switchable-memory characteristics of a silicon nanowire transistor with a dual-gate structure. Figure 1 shows schematic and optical images of our transistor, which consists of a silicon nanowire channel and dual-gate electrodes. On the upper side of the channel region (6 µm long), two gate electrodes (each 2 µm wide) are arranged side by side. The gate electrode located near the p + doped region is named "Gate1 (V G1 )," and the other gate electrode located near the n + doped region is named "Gate2 (V G2 )." Details regarding the fabrication are presented in Experimental Section. Our switchable-memory transistor can be fabricated using conventional CMOS technology, which is clearly advantageous for industrial applications.As shown in Figure 2a, when V DS is swept from −0.1 to 4.1 V and then back to −0.1 V as a function of V G1 and V G2 , our transistor shows bistable I DS -V DS characteristics owing to the similar structures of thin capacitively-coupled thyristor (TCCT) devices [19][20][21] and field-effect diodes. [22,23] Without gate bias voltages, the transistor exhibits ordinary p-n diode characteristics;The switchable-memory operation of a feedback silicon nanowire transistor with a dual-gate structure is demonstrated. The single transistor exhibits volatile memory characteristics with a retention time longer than 3600 s, as well as a switching capability with a subthreshold swing lower than 7 mV dec −1 . A gate-controlled memory window forms around a gate voltage of 0 V owing to the positive feedback loop in the channel region, allowing a program/erase endurance of more th...

Section: Introductionmentioning

confidence: 99%

“…[15] However, electrostatic doping induced by gate bias is required to form a potential well, which is important for the positive feedback loop. [16,17] Although thyristor RAMs (T-RAMs) employ doping regions to form the potential well, external bias is still necessary for T-RAMs to retain the stored charges. [18][19][20] This indispensable bias for holding the stored charges has restricted their use in quasi-nonvolatile memory applications.In this paper, we propose a fully CMOS-compatible p + -n-pn + silicon memory device to enable quasi-nonvolatile memory functionality with high speed, long retention time, and nondestructive reading capability.…”

mentioning

confidence: 99%

Quasi‐Nonvolatile Silicon Memory Device

Adv Materials Technologies

Son

Cho

2020

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Several attempts have been made to store charges in the channel regions of silicon transistors, such as in zero-capacitor random-access memories (Z-RAMs), [7,8] metastable DRAMs (MSDRAMs), [9,10] advanced RAMs (A-RAMs), [11,12] and zeroslope and zero-impact ionization RAMs (Z 2-RAMs). [13,14] Among these, Z 2-RAMs are capable of low-voltage operation with high speed, long retention time, and nondestructive reading capability, because of the positive feedback loop. [15] However, electrostatic doping induced by gate bias is required to form a potential well, which is important for the positive feedback loop. [16,17] Although thyristor RAMs (T-RAMs) employ doping regions to form the potential well, external bias is still necessary for TRAMs to retain the stored charges. [18-20] This indispensable bias for holding the stored charges has restricted their use in quasi-nonvolatile memory applications. In this paper, we propose a fully CMOS-compatible p +-n-pn + silicon memory device to enable quasi-nonvolatile memory functionality with high speed, long retention time, and nondestructive reading capability. Using a well-defined potential well in a p +-n-p-n + silicon structure with a gated n-channel region, our device utilizes holes as majority charge carriers for the positive feedback loop, unlike TRAMs which use electrons as majority charge carriers. Hence, our quasi-nonvolatile silicon memory device can retain the charges stored in the channel region without requiring any external bias, for a long time. In addition, the positive-feedback loop enables low-voltage operation, high speed, and nondestructive reading for quasi-nonvolatile memory applications. 2. Results and Discussion A quasi-nonvolatile silicon memory device consists of p +-n-p-n + regions on a silicon-on-insulator (SOI) substrate (Figure 1a). An SiO 2 /poly-Si gate stack is located on the upper side of the n-channel region. The poly-Si gate modulates the potential barrier of the n-channel region; it controls the hole injection from the p + drain region. The p-channel region is designated to block the electron injection from the n + source region. The channel regions also form potential wells; states "1" and "0" are defined by presence and absence of excess charge carriers in the potential wells, respectively. The corresponding energy band diagrams exhibit the difference in the channel region between the two states (Figure 1b). Barrier-height modulation by carrier accumulation in the potential wells is essential for the positive feedback loop, which allows memory operations. Memory hierarchy among conventional memory technologies is one of the main bottlenecks in modern computer systems; alternative memory technologies are thus necessary for quasi-nonvolatile memory applications. Herein, a fully complementary metal-oxide-semiconductor-compatible quasi-nonvolatile memory composed of p +-n-p-n + silicon on a silicon-on-insulator substrate is presented. The quasi-nonvolatile silicon memory device demonstrates highspeed write capability (≤100 ns), long retenti...